AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 44

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

AD6623
Figure 43. RAM Coefficient Filter, Frequency Response for
WBCDMA
USING THE AD6623 TO PROCESS TWO UMTS CARRIERS
WITH 24 OUTPUT RATE
Overview
The AD6623 may be used to process two UMTS carriers, each
with an output rate of 24× (i.e., 92.16 MSPS). The AD6623
configuration used to accomplish this consists of using two pro-
cessing channels in parallel to process each UMTS carrier. The
ideology behind the parallel processing approach is that each
channel operates on half of the input samples, processing every
other sample. The reason is that the serial input data rate is limited
to 3.25 MSPS for 16-bit I and 16-bit Q data (104 MSPS/32).
The first channel of each pair begins processing the first input
sample immediately. The second channel begins processing after a
specific delay so that the two channels essentially will be operating
180 degrees out of phase with each other. Since each channel
processes only half the input samples and thus receives input data
at half the original rate, each channel has twice the original amount
of time available for processing. This in turn makes available
twice the original number of taps, resulting in much improved
digital filtering capability. To maximize the number of available
FIR filter taps, the highest possible input rate should be used.
9/16/02 12:30 PM_TG
Figure 44. RCF and CIC, Frequency Response for WBCDMA
–100
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–100
10
–10
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–90
0
10
0
0
0
1000
1000
FILTER
IDEAL
2000 3000 4000 5000 6000 7000 8000 9000 10000
2000 3000 4000 5000 6000 7000 8000 9000 10000
AD6623 RESPONSE
COMPOSITE
kHz
kHz
CIC ROLLOFF
–44–
Therefore, this application note assumes an input sample rate of
3.84 MSPS and an output data rate of 24× (i.e., 92.16 MSPS),
which in conjunction with the 1× input rate (assumes two channels
used per carrier at 1.92 MSPS) results in a total decimation value
of 24. Since two AD6623 channels will be used for each carrier,
each channel will operate with a total interpolation of forty-eight,
resulting in a total of 24 taps for the FIR filter. All channels must
be configured with the same FIR filter coefficients, decimation
and interpolation values, and scaling values.
Configuring the AD6623
The Serial Input Data ports need run at 1.92 MSPS by using
f
In order to properly process a UMTS channel across two channels
the channels need to be synchronized. The channel starts will be
delayed by precise input clock periods, and the NCO’s will be
independently phased to account for starting channels out of
phase. The final output summation stage adds data from separate
channels together.
It should be noted that all serial output ports must be configured for
Serial Bus Master Mode, since SCLKs cannot be run at 92.16 MHz
in slave mode.
When initiating carrier processing, care should be taken to ensure
that both the primary and secondary processing channels are
started with precise relative timing (preferably by a pulse on one
of the SYNC pins). The device is configured with the following
filtering parameters:
AD6623 Register Configuration
To process two UMTS carriers with 24× output rate, the AD6623
must be properly configured. The following sections describe
the required register settings for this configuration. Interpolation,
decimation, and scaling values specified for the following regis-
ters were used to obtain the reference filter response shown in
the Performance section of this data sheet. Other registers may
be set as needed for any individual application.
0, 1: bit must be set to zero or one as indicated.
‘u’: bit is dependent on the user’s application, but must be
‘x’: bit can be set at user’s discretion, regardless of the channel used.
Coefficient Memory (0x900–0x9FF, Bits 15:0)
Each pair of processing channels must be assigned the same
FIR filter coefficients. Twenty-four taps must be used, typically
loaded into addresses 0x900-0x9FF.
SCLK
L
N
L
L
M
SCLK = 92.16
For registers with bit fields, the following symbols are used:
RCF
CIC5
CIC2
TAPS
CIC2
= 92.16 MSPS, with SCLK divider = 0 (0x0D, Bits 4- 0 = 0).
the same for both channels of a processing pair.
= 6
= 8
= 1
= 24
= 1
REV. A