AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 45

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

The FIR filter coefficients for the reference filter are:
–181
–101
24803
2420
–816
–4461
14446
1729
–1084
–5366
1588
–209
–209
1588
–5366
–1084
1729
14446
–4461
–816
2420
24803
–101
–181
Start Sync Control Register (0xn00, Bits 17:16)
The settings in this register must be the same for each pair of
processing channels.
Start Holdoff Counter (0xn00, Bits 15:0)
The secondary channel of each processing pair needs to be
configured such that it begins processing 180 degrees out of phase
with the primary channel. The Start Holdoff Counter (SHC) of
the secondary channel is set to the value of the primary channel
plus LTOT/2, where LTOT is the overall channel interpolation.
For example, in the case of LTOT = 48, the primary channel of
each processing is set to two, while the secondary channel’s
Start Holdoff Counter is set to twenty-six.
NCO Frequency Registers (0xn02, Bits 31:0)
Each pair of processing channels must be assigned the same
NCO Frequency Register values.
NCO Frequency Holdoff Counter (0xn03, Bits 15:0)
Each pair of processing channels must be assigned the same
NCO Holdoff Counter value.
NCO Phase Offset Register (0xn04, Bits 15:0)
The NCO of the secondary channel must have its initial phase
set such that, when it begins processing, its phase is equal to
REV. A
SCC
2
ndChannel
=
SCC
1
stChannel
+
L
TOT
2
(34)
–45–
that of the primary channel’s phase. The equation is given by:
where
NCO Phase Offset Update Holdoff (0xn05, Bits 15:0)
Each pair of processing channels must be assigned the same
NCO Phase Offset Update Holdoff value.
CIC Scale (0xn06, Bits 4:0)
Each pair of processing channels must use a value of seventeen
for this register (S
rCIC2 Decimation-1 (0xn07, Bits 8:0)
Each pair of processing channels must use a value of zero for
this register (rCIC2 decimation = 0).
rCIC2 Interpolation-1 (0xn08, Bits 7:0)
Each pair of processing channels must use a value of zero for
this register (rCIC2 interpolation = 0).
CIC5 Interpolation-1 (0xn09, Bits 7:0)
Each pair of processing channels must use a value of seven for
this register (CIC5 interpolation = 7).
RCF Number of Taps-1 (0xnA0, Bits 7:0)
Each pair of processing channels must use a value of twenty-
three for this register (NRCF-1 = 23).
RCF Coefficient Offset (0xn0B, Bits 7:0)
Each processing channel must specify the offset of the address
where its coefficients begin (typically zero).
RCF Mode (0xn0C, Bits 9:4)
Each pair of processing channels must set all these bits to zero.
RCF Mode (0xn0C, Bits 3:0)
Each pair of processing channels must be assigned the same
number of taps per phase which in this case is four.
Serial Data Frame Input Select (0xn16, Bits 7:6)
The secondary channel of each processing pair needs to be
configured such that it begins processing data after the primary
channel’s Frame end. This is done by setting the Serial Data
Frame Input Select bits high (Bits 7:6 = 11).
Serial Data Frame Output Select (0xn16, Bits 5)
The primary channel of each processing pair needs to be
configured such that it is configured for Serial Data Frame
Request (Bit 5 = 0).
Serial Clock Slave (0xn16, Bits 4)
Each pair of processing channels must be configured in Master
mode (Bit 4 = 0).
Performance
The filter performance of the AD6623’s dual-channel processing
approach is shown in Figure 45. This filter uses 24 taps, with
RCF interpolation of 6, CIC5 interpolation of 8, and rCIC2
interpolation and decimation of 1 and 1, respectively. The near
rejection at 5 MHz is 65 dBc, and rejection at 10 MHz is 80 dBc,
with a passband ripple of 0.25 dB. The register settings implement-
ing this filter are outlined in the AD6623 Register Configuration
section of this technical note.
NCOPhaseOffset
round() returns the nearest integer of its argument,
frac() returns the fractional part of its argument,
f
f
NCO
SAMP
is the desired NCO frequency, and
is the desire output sample rate.
CIC
=
round frac
= 12).







L
TOT
2
⋅
f
f
SAMP
NCO

 ⋅

AD6623
2
16




(35)