AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 6

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

AD6623
MICROPROCESSOR PORT TIMING CHARACTERISTICS
Parameter (Conditions)
MICROPROCESSOR PORT, MODE INM (MODE = 0)
MODE INM Write Timing:
t
t
t
t
t
t
t
MODE INM Read Timing:
t
t
t
t
t
t
t
t
MICROPROCESSOR PORT, MOTOROLA (MODE = 1)
MODE MNM Write Timing:
t
t
t
t
t
t
t
t
MODE MNM Read Timing:
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
Specifications subject to change without notice.
SC
HC
HWR
SAM
HAM
DRDY
ACC
SC
HC
SAM
HAM
ZOZ
DD
DRDY
ACC
SC
HC
HDS
HRW
SAM
HAM
DDTACK
ACC
SC
HC
HDS
SAM
HAM
ZD
DD
DDTACK
ACC
All Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.
C
Specification pertains to control signals: RW, (WR), DS, (RD), CS.
LOAD
= 40 pF on all outputs (unless otherwise specified).
Control
Control
WR(RW) to RDY(DTACK) Hold Time
Address/Data to WR(RW) Setup Time
Address/Data to RDY(DTACK) Hold Time
WR(RW) to RDY(DTACK) Delay
WR(RW) to RDY(DTACK) High Delay
Control
Control
Address to RD(DS) Setup Time
Address to Data Hold Time
Data Three-State Delay
RDY(DTACK) to Data Delay
RD(DS) to RDY(DTACK) Delay
RD(DS) to RDY(DTACK) High Delay
Control
Control
DS(RD) to DTACK(RDY) Hold Time
RW(WR) to DTACK(RDY) Hold Time
Address/Data to RW(WR) Setup Time
Address/Data to RW(WR) Hold Time
DS(RD) to DTACK(RDY) Delay
RW(WR) to DTACK(RDY) Low Delay
Control
Control
DS(RD) to DTACK(RDY) Hold Time
Address to DS(RD) Setup Time
Address to Data Hold Time
Data Three-State Delay
DTACK(RDY) to Data Delay
DS(RD) to DTACK(RDY) Delay
DS(RD) to DTACK(RDY) Low Delay
3
3
3
3
3
3
3
3
to ↑CLK Setup Time
to ↑CLK Hold Time
to ↑CLK Setup Time
to ↑CLK Hold Time
to ↑CLK Setup Time
to ↑CLK Hold Time
to ↑CLK Setup Time
to ↑CLK Hold Time
–6–
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
1, 2
Test
Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Min
4.5
2.0
8.0
3.0
2.0
4.0
4 × t
4.5
2.0
3.0
2.0
4.0
8 × t
4.5
2.0
8.0
8.0
3.0
2.0
4 × t
4.0
2.0
8.0
3.0
2.0
8 × t
CLK
CLK
CLK
CLK
AD6623AS
Typ
5 × t
10 × t
5 × t
10 × t
CLK
CLK
CLK
CLK
Max
9 × t
13 × t
9 × t
13 × t
CLK
CLK
CLK
CLK
REV. A
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns