AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet
AD6652BC/PCB
Specifications of AD6652BC/PCB
Related parts for AD6652BC/PCB
AD6652BC/PCB Summary of contents
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FEATURES SNR = 150 kHz bandwidth (to Nyquist @ 61.44 MSPS) Worst harmonic = 83 dBc (to Nyquist @ 61.44 MSPS) Integrated dual-channel ADC: Sample rates MSPS IF sampling frequencies to 200 MHz Internal ...
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AD6652 TABLE OF CONTENTS Product Description......................................................................... 4 Product Highlights ....................................................................... 4 Specifications..................................................................................... 5 Recommended Operating Conditions ...................................... 5 ADC DC Specifications............................................................... 5 ADC Switching Specifications.................................................... 5 ADC AC Specifications ............................................................... 6 Electrical Characteristics ............................................................. 7 General Timing Characteristics ................................................. 8 ...
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Parallel Output Ports.......................................................................50 Channel Mode .............................................................................50 AGC Mode ...................................................................................51 Master/Slave PCLK Modes ........................................................52 Parallel Port Pin Functions ........................................................52 Link Port...........................................................................................53 Link Port Data Format ...............................................................53 Link Port Timing.........................................................................53 TigerSHARC Configuration ......................................................54 External Memory Map ...................................................................55 Access Control Register (ACR) .................................................56 ...
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AD6652 PRODUCT DESCRIPTION The AD6652 is a mixed-signal IF to baseband receiver consisting of dual 12-bit 65 MSPS ADCs and a wideband multimode digital downconverter (DDC). The AD6652 is designed to support communications applications where low cost, small size, and ...
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SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Table 1. Parameter AVDD VDD VDDIO T AMBIENT ADC DC SPECIFICATIONS AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted. ...
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AD6652 ADC AC SPECIFICATIONS AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference. Table 4. Parameter (Conditions) 1 SIGNAL-TO-NOISE RATIO (WITHOUT HARMONICS) Analog Input Frequency 10.4 MHz ...
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ELECTRICAL CHARACTERISTICS AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted. Table 5. Parameter (Conditions) LOGIC INPUTS Logic Compatibility Logic 1 Voltage Logic 0 ...
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AD6652 GENERAL TIMING CHARACTERISTICS All timing specifications valid over VDD range of 2. 2.75 V and VDDIO range of 3 3.6 V. CLOAD = all outputs, unless otherwise specified. Table 6. Parameter (Conditions) ...
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MICROPROCESSOR PORT TIMING CHARACTERISTICS All timing specifications valid over VDD range of 2. 2.75 V and VDDIO range of 3 3.6 V. CLOAD = all outputs, unless otherwise specified. Table 7. MICROPROCESSOR PORT, ...
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AD6652 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter ELECTRICAL AVDD Voltage VDD Voltage VDDIO Voltage AGND, DGND ADC VINA, VINB Analog Input Voltage ADC Digital Input Voltage ADC OTRA, OTRB Digital Output Voltage ADC VREF, REFA, REFB Input Voltage DDC Digital ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 9. BGA Pin Configuration (Top View DGND PA7_LA7 A2 PA6_LA6 PACH0_ Do Not B PA4_LA4 LACLK A0 Connect OUT PA9 PA3_LA3 A1 PACH1_ D ...
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AD6652 Table 10. Pin Function Descriptions Pin No. POWER SUPPLY A13, B13, C13, D13, E13, F13, G13, H13, J13, K13, L13, M13, N13, P13, R13, T13, A14, B14, C14, D14, E14, M14, N14, P14, R14 D4, D5, D6, D7, E4, ...
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Pin No. Mnemonic DDC OUTPUTS B11 LIA C11 LIA C12 LIB P8 LIB 2 B3 PACH0_LACLKOUT 2 R2 PACH0_LBCLKOUT PA[7:0]_LA[7:0] F1, D1, D2, C2, B2, E2, A4, A2 P2, R3, N3, PB[7:0_LB[7:0] M2, M3, T3, L1, L2 E1, C1, F3, ...
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AD6652 TYPICAL PERFORMANCE CHARACTERISTICS –1dBFS IN –10 SNR = 90dB (200kHz BW) –20 32k FFT –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –300 –200 –100 0 100 FREQUENCY (kHz) Figure 2. ...
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ENCODE = 61.44MSPS – –7dBFS IN –20 32k FFT –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –4 –3 –2 – FREQUENCY (MHz) Figure 8. Two Tones at 15 MHz ...
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AD6652 –1dBFS ANALOG INPUT FREQUENCY (MHz) Figure 14. Noise vs. Analog Frequency –1dBFS 25° 100 ...
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DDC TIMING DIAGRAMS CLK LIA, LIB LIA, LIB RESET SYNCA SYNCB SYNCC SYNCD CLK PCLK CLK PCLK t CLK t CLKL t CLKH t DLI Figure 17. Level Indicator Output Switching Characteristics t RESL Figure 18. Reset Timing Requirements CLK ...
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AD6652 PCLK PxACK PCLK PxREQ t SPA PxACK Px[15:0] PCLK PxACK PxREQ Px[15:0] PCLK PxACK t HPA t SPA Figure 22. Master Mode PxACK to PCLK Setup and Hold Characteristics t SPA t DPP DATA 1 DATA 2 Figure 23. ...
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PCLK PxREQ t SPA PxACK t Px[15:0] DATA 1 Figure 26. Slave Mode PxACK to PCLK Switching Characteristics PCLK PxACK t DPREQ PxREQ Px[15:0] Figure 27. Slave Mode PxREQ to PCLK Switching Characteristics PCLK LxCLKOUT Figure 28. LxCLKOUT to PCLK ...
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AD6652 LxCLKOUT WAIT ≥ 6 CYCLES ONE TIME CONNECTIVITY CHECK LxCLKIN Lx[7:0] LxCLKOUT Lx[7:0] t FDLCLKDAT CLK RD (DS) WR (R/W) CS A[2:0] D[7:0] RDY (DTACK) NOTES t 1. ACC FROM RDY ...
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CLK (DS) WR (RW SAM A[2:0] VALID ADDRESS D[7:0] t DRDY RDY (DTACK) t ACC NOTES t 1. ACCESS TIME DEPEND S ON THE ADDRESS ACC FROM RDY. t ...
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AD6652 CLK DS (RD) R/W (WR) CS A[2:0] D[7:0] DTACK (RDY) NOTES t 1. ACC FROM THE THE ACC HDS t SAM VALID ADDRESS VALID DATA t ...
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TERMINOLOGY Crosstalk Coupling onto one channel being driven by a (−0.5 dBFS) signal when the adjacent interfering channel is driven by a full-sc signal. Measurement includes all spurs resulting from both direct coupling and mixing components. IF Sampling (Undersampling) Due ...
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AD6652 THEORY OF OPERATIO N The AD6652 has two analog input channels, four digital filter- ing channels, and two digital output channels. The IF input signal passes through several stages before it appears at th output port( well-filtered, ...
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For best dynamic performance source impedances driving the differential analog inputs should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC 5pF VINA ...
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AD6652 Internal Reference Connection A comparator within the AD6 652 detects the potential at the SENSE pin and configures t he reference into four possible states, which are summarized in Table 11. If SENSE is grounde the reference amplifier switch ...
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External Reference Operation An external reference voltage can be used to enhance the gain accuracy of the ADC or improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) might be necessary to reduce ...
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AD6652 Clock Input Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result can be sensiti to ACLK clock duty cycle. Commonly a 5% tolerance is required on the ...
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DIGITAL DOWNCONVERTER ARCHITE DATA INPUT MATRIX The digital downconverter (DDC) section features dual high speed 12-bit input ports that are capable of crossbar multiplex- ing of data to the four processing channels that follow the inpu matrix. In addition, a ...
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AD6652 SIGNAL OF INTEREST IMAGE – –f /2 –3 /8 –5 / AFTER FREQUENCY TRANSLATION – –f /2 –3 /8 –5 / FREQUENCY TRANSLATION (FOR EXAMPLE, ...
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CONTROL REGISTER AND The following sections make frequent references to program- mable registers and the memory mapping structure of the AD6652. A good overview of the control registers and memory mapping structure is found beginning in the External Mem Map ...
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AD6652 the input condition falls below the lower progra threshold. To provide hysteresis, a dwell time register (see Table 28) is available to hold off switching of the control line for a predetermined number of clocks. Once the input condition ...
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NUMERICALLY CON TROLLED OSCILLATOR FREQUENCY TRANSLATION TO BASEBAND This processing stage comprises a digital tuner consisting two multipliers, I and Q, and a 32-bit complex numerically contr lled oscillator (NCO). Each channel of the AD6652 has o an inde pendent ...
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AD6652 Clear Phase Accumulator on Hop When Bit 3 is logic high, the NCO phase acc (set to all zeros) at the beginning of the next frequency change. This ensures a consistent phase of the NCO on each hop by ...
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SECOND-ORDER rCIC FILTE The rCIC2 filter is a second-order resampling cascaded integrator comb filter. The resampler is implemented using a unique technique, which does not require the use of a high- speed clock, thus simplifying the design and saving power. ...
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AD6652 rCIC2 OUTPUT LEVEL After the prop er scaling factor has been determined, the output level from the rCIC2 stage can be determined using the following equation × rCIC 2 OL input rCIC 2 × ...
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FIFTH-ORDER CIC FILTER The fourth signal processing stage, CIC5, implements a sharp fixed-coefficient, decimating filter than rCIC2. The input rate to this filter The maximum input rate is given by the SAMP2 following equation. N equals two ...
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AD6652 RAM COEFFICIENT FILTER The final signal processing stage is a sum-of-products decimat- ing filter with programmable coefficients. A simplified block diagram is shown in Figure 49. The data memories I-RAM an Q-RAM store the 160 most recent complex samples ...
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RCF OUTPUT SCALE FACTOR AND CONTROL REGISTER Register 0xA4 is a compound register used to configure several aspects of the RCF register. Use Bits 3–0 to set the scale of the fixed-point output mode. This scale value can also be ...
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AD6652 INTER POLATING HALF-BAND FILTERS The AD6652 has two interpolating half-band FIR filters th immediately precede the two digital AGCs a RCF channel outputs. Each interpolating half-band takes 16-bit I and 16-bit Q data from the preceding RCF and output ...
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AUTOMATIC GAIN CONTROL The AD6652 is equipped with two independent automatic control (AGC) loops for direct interface with a Rake receive Each AGC circuit has range important that the decimating filters of the AD6652 preceding ...
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AD6652 Because the number of average samples must be an integer multiple of the decimation value, only the multiple number programmed. This number is programmed in Ou Port Control Registers 0x10:1–0 and 0x18:1–0. These ...
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Though the user defines the open loop po and gain K , they directly impact the placement of the clo loop poles and filter characteristics. These closed loop pole P are the roots of the denominator of the above ...
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AD6652 for averaging and decimating the update samples and taking their square root to f ind rms samples desired signal level mode. In place of the request de sired signal level, a desired cl ipping level is subtracted, ...
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USER-CONFIGURABLE BUILT-IN SELF-TE The AD6652 includes two built-in test features to test the integrity of each channel. The first is a RAM BIST (built-in test), w hich is intended to test the integrity of the high speed random access memory ...
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AD6652 CHANNEL/CHI P SYNCHRONIZATION The AD6652 has been designed to easily synchronize two common functions: Start and Hop. While the AGC stage can also be synchronized not accommo soft-sync and pin-sync signals normally associated with AD6652 synchronization. Start ...
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AD6652 HARDWARE AND SOFTWARE SYNC CONTROL FOR ONE PROCESSING CHANNEL PIN SYNC_EN A* SYNCA PIN PIN SYNC_EN B* SYNCB PIN PIN SYNC_EN C* SYNCC PIN PIN SYNC_EN D* SYNCD PIN * FROM EXTERNAL MEMORY ADDRESS REGISTER 4:3-0 NOTE: ALL CIRCUITRY ...
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AD6652 Start with Pin Sync The AD6652 provides four SYNC pins and D, which are used for very accurate channel synchronization. Each DDC channel can be programmed to respond to any or all four syn pins. Synchronization ...
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Hop with Pin Sync Just as in the start function, the AD6652 provides four SYNC pins and D, which are used for very accurate channe synchronization. Each DDC channel can be programmed to respond to any or ...
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AD6652 PARALLEL O UTPUT PORTS The AD6652 incorporates two independent 16-bit parallel po for output data transfer. To minimize package ball count, the eight LSBs of each 16-bit port are shared with their respective DSP link port data bits (see ...
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PCLKn PxACK t DPREQ PxREQ t DPP I[15:0] Px[15:0] t DPIQ PxIQ t DPCH PxCH[1:0] = PxCH[1:0] Channel # Figure 55. Channel Mode Interleaved Format The 8-bit concurrent format provides 8 bits of I data and 8 bits of Q ...
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AD6652 PCLKn PxACK t DPREQ PxREQ t DPP Px[15:0] I[15:0] t DPIQ t DPCH PxIQ PxCH[0] = AGC # PxCH[1:0] PxCH[ Figure 58. AGC with RSSI Word MASTER/SL AVE PCLK MODES Th e paralle l ports operate in ...
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LINK PORT The AD6652 has two configurable link ports that provide a seamless data interface with the TigerSHARC TS-101 series DSP. Each link port allows the AD6652 to write output data to the receive DMA channel in the TigerSHARC for ...
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AD6652 The length of the wait before data transm programmable value in the link port control registers (0x1B and 0x1D Bits 6–3). This value allows the AD6652 PCLK TigerSHARC PCLK to be run at different rates and phase. ⎛ f ...
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EXTERNAL MEMORY MAP The external memory map is the only way to gain access to the four channel address register pages and the output port control register page. This set of eight registers is shown in Table 22. These registers ...
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AD6652 ACCESS CONTROL REGISTER (ACR) External Address 7 The ACR specifies certain programming characteristics such as autoincrement or broadcast, which are to be applied to the incoming instructions, and selects which channel(s) are to be programmed microport ...
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PIN_SYNC CONTROL REGISTER Exte rnal Address 4 This write-only PI N_SYNC control register. B its 3–0 of this register are the PIN SYNC_EN control bits. T hese bits can be writt the controller ...
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AD6652 A[9:8] FROM BITS [1:0] OF ACR, EXTERNAL ADDRESS 7 2 *CHANNEL DECODER CAN BE OVERR Figure 63. 0x81: Soft_SYNC Register This register is used to initiate software-generated SYNC events through the microport. It mimics the programming of Bits 4 ...
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NCO control register at Channel Address 0x88. When this bit is low, then the phase accumulator of the NCO is not cleared, but starts to add the new NCO frequency word to the accumulator as soon as the SYNC occurs. ...
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AD6652 Channel Address Register A4 RCF Control Register A5 BIST Signature for I Path A6 BIST Signature for Q Path A7 BIST Outputs to Accumulate A8 RAM BIST Control Register A9 Output Control Register 0x87: NCO Phase Offset Register This ...
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M must be chosen larger than L , and both must be rCIC2 rCIC2 chosen such that a suit able rCIC2 scalar can be chosen. For deta ils, see the Second -Order RCIC Filter s 0x9 1: rCIC2 Interpol ation ...
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AD6652 individual magnitudes. When this bit is 1, then the I and Q data is a complex floating-point number, where I and Q use a single exponent that is determined based on the maximum magnitude Bit ...
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INPUT PORT CONTROL REGISTERS The i npu control registers ena ble variou f eat ures used p rimarily for level con trol. Dep m ode of operation four different signal paths can be m onitored ...
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AD6652 Table 28. M emory Ma p for Input Port Control Registers Channel Addre ss Register 00 Lower Threshold A 01 Upper Threshold A 02 Dwell Time A 03 Gain Range A Control 04 Lower Threshold B 05 Upper Threshold ...
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CHANNEL INTERLEAVE PROCESSED DATA FROM RCFS ENABLE/DISABLE (0x08:3, 0x09:2) Figure 64. Block Diagram of an AGC Stage Showing the Components and Signal Routing Options Note: The hold-off counter o f AGC A shares the PIN SYNC assigned to DDC processing ...
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AD6652 Table 29. Memory Map for Output Port Control Regist Address Register 08 LHB A Control Register 09 LHB B Control Register 0A AGC A Control Register 0B AGC A Hold-Off Counter 0C AGC A Desired Level 0D AGC A ...
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Address Register 13 AGC B Hold-Off Counter 14 AGC B Desired Level 15 AGC B Signal Gain 16 AGC B Loop Gain 17 AGC B Pole Location 18 AGC B Average Samples 19 AGC B Update Decimation 1A Parallel A ...
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AD6652 Address Register 1E Port Clock Control 1 Set the LHB A and/or LHB B enable bits to logic low only when the entire block functions shut down. 2 PCLK boots as a slave. 0x0E: AGC A Loop Gain This ...
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If this bit is set, only the f irst sync high is recognized and succeeding sync events are ignored until Bit 1 is reset. Bit 0 is used to bypass the AGC section, when it is set. When the AGC ...
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AD6652 Bit 0 selects which data i s output on Link Port A. When Bit Link Port A outputs data from the the format specified by Bit 1. When Bit Link Port A outputs ...
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Port Clock Control Bit 0 determines whether PCLK is supplied externally by the user or derived internally in the AD6652. If PCLK is derived internally from CLK (Bit output through the PCLK pin as ...
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AD6652 Internal Write Access bits of data (as needed) can be written by the following process. Any high order bytes that are needed are written to th corresponding data registers defined in the external mem map 3-bit ...
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APPLICATIONS AD6652 RECEIVER APPLICATIONS One CDMA2000 IF Carrier with No External Analog Filtering Code Division Multiple Access depends upon a unique code sequence that modulates the IF carrier along with the payload data. This permits multiple signals to be transmitted ...
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AD6652 7. Serial port control and serial data output are not available on this part. 8. Broadcast and programming multiple AD6652 parts using the same microport control/data signals does not work for input/output port control registers (Addresses 0x00 to 0x1E). ...
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AD6652 EVALUATION BOARD AND SOFTWARE The AD6652 evaluation board kit contains a fully populated AD6652 PCB, schematic diagrams, operating software, comprehensive instruction manual, and digital filter design software. XTAL U201 OSCILLATOR J205 J206 J202 T201 INPUT A CLK ANALOG AD6652 ...
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... OUTLINE DIMENSIONS 1.85* 1.71 1.40 ORDERING GUIDE Model Temperature Range AD6652BBC −40°C to +85°C AD6652BC/PCB © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 17.00 BSC SQ BALL A1 INDICATOR 15.00 BSC SQ 1.00 ...