ADL5602ARKZ-R7 Analog Devices Inc, ADL5602ARKZ-R7 Datasheet - Page 11

IC AMP HBT INGAP 4GHZ SOT89

ADL5602ARKZ-R7

Manufacturer Part Number
ADL5602ARKZ-R7
Description
IC AMP HBT INGAP 4GHZ SOT89
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADL5602ARKZ-R7

Gain
19.5dB
Rf Type
Cellular, CATV
Current - Supply
89mA
Frequency
50MHz ~ 4GHz
Noise Figure
3.3dB
P1db
19.3dBm
Package / Case
SC-62, SOT-89, TO-243 (3 Leads + Tab)
Test Frequency
2GHz
Voltage - Supply
5V
Frequency Range
50MHz To 4GHz
Noise Figure Typ
4.2dB
Power Dissipation Pd
450mW
Supply Current
89mA
Supply Voltage Range
4.5V To 5.5V
Manufacturer's Type
Broadband Amplifier
Number Of Channels
1
Frequency (max)
4GHz
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Package Type
SOT-89
Mounting
Surface Mount
Pin Count
3 +Tab
Noise Figure (typ)
4.2@4000MHzdB
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
ADL5602ARKZ-R7TR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADL5602ARKZ-R7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
BASIC CONNECTIONS
The basic connections for operating the ADL5602 are shown in
Figure 15. Recommended components are listed in Table 5. The
input and output should be ac-coupled with appropriately sized
capacitors (device characterization was performed with 0.1 μF
capacitors). A 5 V dc bias is supplied to the amplifier through
the bias inductor connected to RFOUT (Pin 3). The bias voltage
should be decoupled using a 1 μF capacitor, a 1.2 nF capacitor,
and a 68 pF capacitor.
Table 5. Recommended Components for Basic Connections
Frequency (MHz)
50 to 4000
RFIN
0.1µF
C1
1
Figure 15. Basic Connections
ADL5602
(2)
2
C1
0.1 μF
3
GND
C2
0.1 μF
VCC
1.2nF
68pF
L1
470nH
1µF
C6
C5
C4
0.1µF
C2
L1
470 nH (Coilcraft 0603LS-NX or equivalent)
RFOUT
Rev. 0 | Page 11 of 16
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
Figure 16 shows the recommended land pattern for the ADL5602.
To minimize thermal impedance, the exposed paddle on the
package underside should be soldered down to a ground plane
along with Pin 2. If multiple ground layers exist, they should be
stitched together using vias. For more information on land
pattern design and layout, refer to AN-772 Application Note, A
Design and Manufacturing Guide for the Lead Frame Chip Scale
Package (LFCSP).
5.56mm
0.86mm
Figure 16. Recommended Land Pattern
0.20mm
1.50mm
3.00mm
1.80mm
C4
68 pF
3.48mm
C5
1.2 nF
0.62mm
1.27mm
ADL5602
C6
1 μF

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