AD8351ARMZ Analog Devices Inc, AD8351ARMZ Datasheet - Page 13

IC DIFF AMP RF/IF LOWDIST 10MSOP

AD8351ARMZ

Manufacturer Part Number
AD8351ARMZ
Description
IC DIFF AMP RF/IF LOWDIST 10MSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD8351ARMZ

Gain
26dB
Rf Type
General Purpose
Current - Supply
28mA ~ 32mA
Frequency
10MHz ~ 2.5GHz
P1db
13.5dBm
Package / Case
10-MSOP, Micro10™, 10-uMAX, 10-uSOP
Test Frequency
10MHz
Voltage - Supply
3 V ~ 5 V
Frequency Range
2.2GHz
Power Dissipation Pd
320mW
Supply Current
28mA
Supply Voltage Range
3V To 5.5V
Rf Ic Case Style
MSOP
No. Of Pins
10
Number Of Channels
1
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Package Type
MSOP
Mounting
Surface Mount
Pin Count
10
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Noise Figure
-
Lead Free Status / Rohs Status
Compliant

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It is important to ensure that all I/O, ground, and R
be kept as short as possible. In addition, it is required that the
ground plane be removed from under the package. Due to the
inverse relationship between the gain of the device and the value
of the R
result in gain-peaking at high frequencies. Following the precau-
tions outlined in Figure 12 will help to reduce parasitic board
capacitance, thus extending the device’s bandwidth and reducing
potential peaking or oscillation.
TRANSMISSION LINE EFFECTS
As noted, stray transmission line capacitance, in combination with
package parasitics, can potentially form a resonant circuit at high
frequencies, resulting in excessive gain peaking. R
lines connecting the input and output networks should be designed
such that stray capacitance is minimized. The output single-ended
source impedance of the AD8351 is dynamically set to a nominal
value of 75 Ω. Therefore, for a matched load termination, the
characteristic impedance of the output transmission lines should be
designed to be 75 Ω. In many situations, the final load impedance
may be relatively high, greater than 1 kΩ. It is suggested that the
board be designed as shown in Figure 12 for high impedance load
conditions. In most practical board designs, this requires that
the printed-circuit board traces be dimensioned to a small width
(~5 mils) and that the underlying and adjacent ground planes are
far enough away to minimize capacitance.
Typically the driving source impedance into the device will be
low and terminating resistors will be used to prevent input reflec-
tions. The transmission line should be designed to have the
appropriate characteristic impedance in the low-Z region. The
high impedance environment between the terminating resistors
and device input pins should not have ground planes under-
neath or near the signal traces. Small parasitic suppressing
resistors may be necessary at the device input pins to help desensitize
REV. B
WAVEGUIDE
COPLANAR
OR STRIP
Figure 12. General Description of Recommended
Board Layout for High-Z Load Conditions
G
resistor, any parasitic capacitance on the R
AGND
R
R
T
T
BALANCED
R
R
SOURCE
IP
IP
R
1
2
3
4
5
G
50
50
R
R
S
S
50
50
CABLE
CABLE
10
9
8
7
6
F
50
50
transmission
G
R
R
G
AGND
T
T
port traces
R
R
Figure 14. Test Circuit
ports can
OP
OP
0.1nF
0.1nF
Hi-Z
AD8351
DUT
–13–
100nF
100nF
(“de-Q”) the resonant effects of the device bond wires and
surrounding parasitic board capacitance. Typically, 25 Ω series
resistors (size 0402) adequately de-Q the input system without a
significant decrease in ac performance.
Figure 13 illustrates the value of adding input and output series
resistors to help desensitize the resonant effects of board parasitics.
Overshoot and undershoot can be significantly reduced with the
simple addition of R
Figure 13. Step Response Characteristics with and
without Input and Output Parasitic Suppression Resistors
CHARACTERIZATION SETUP
The test circuit used for 150 Ω and 1 kΩ load testing is provided
in Figure 14. The evaluation board uses balun transformers to
simplify interfacing to single-ended test equipment. Balun effects
need to be removed from the measurements in order to accu-
rately characterize the performance of the device at frequencies
exceeding 1 GHz.
The output L-pad matching networks provide a broadband
impedance match with minimum insertion loss. The input
lines are terminated with 50 Ω resistors for input impedance
matching. The power loss associated with these networks needs
to be accounted for when attempting to measure the gain of the
device. The required resistor values and the appropriate inser-
tion loss and correction factors used to assess the voltage gain
are provided in Table II.
Load
Condition
150 Ω
1 kΩ
R
LOAD
R1
R1
Table II. Load Conditions Specified Differentially
–0.5
–1.0
–1.5
1.5
1.0
0.5
0
0
R2
R2
NO R
50
50
R1
43.2 Ω
475 Ω
IP
CABLE
CABLE
OR R
IP
and R
OP
1
R
IP
R2
86.6 Ω
52.3 Ω
50
50
OP
= R
50
EQUIPMENT
.
R
OP
OP
TIME (ns)
TEST
= 25
= 25
2
Total
Insertion
Loss
5.8 dB
15.9 dB
3
AD8351
20 log (S21)
Conversion
Factor
to 20 log (A
7.6 dB
25.9 dB
4
V
)

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