ATA5723-DK Atmel, ATA5723-DK Datasheet
ATA5723-DK
Specifications of ATA5723-DK
Related parts for ATA5723-DK
ATA5723-DK Summary of contents
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... Fully Integrated LC-VCO and PLL Loop Filter • Very High Sensitivity with Power Matched LNA – ATA5723/ATA5724: –107 dBm, FSK, BR_0 (1.0 kBit/s to 1.8 kBit/s), Manchester, BER 10E-3 –113 dBm, ASK, BR_0 (1.0 kBit/s to 1.8 kBit/s), Manchester, BER 10E-3 – ATA5728: – ...
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... Description The ATA5723/ATA5724/ATA5728 is a multi-chip PLL receiver device supplied in an SSO20 package. It has been specially developed for the demands of RF low-cost data transmission sys- tems with data rates from 1 kBit kBbit/s in Manchester or Bi-phase code. Its main applications are in the areas of keyless entry systems, tire pressure monitoring systems, teleme- tering, and security technology systems ...
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... Figure 1-2. Block Diagram CDEM RSSI SENS AVCC AGND DGND DVCC LNAREF LNA_IN LNA LNAGND 9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 FSK/ASK Dem_out Demodulator and Data Filter RSSI Limiter out RSSI IF Sensitivity Amp. reduction and Control Logic 4. Order MHz 0 Standby LPF Logic f = 2.2 MHz ...
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... Crystal oscillator XTAL connection 1 Crystal oscillator XTAL connection 2 Digital power supply Selecting 315 MHz/other versions Low: 315 MHz version (ATA5723) High: 433 MHz/868 MHz versions (ATA5724/ATA5728) Bit clock of data stream Digital ground Selects polling or receiving mode; Low: receiving mode, High: polling mode Data output/configuration input 9106E– ...
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... XTO Peripherals DVCC XTAL2 XTAL1 TEST3 TEST2 is determined by the RF input frequency f LO – ATA5723/ATA5724/ATA5728 for the mixer using a fully integrated synthesizer with = f /2 (868 MHz and 433 MHz versions) REF XTO = f /4 for 433 MHz and 315 MHz versions). LO VCO is determined, f ...
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... 947.9 kHz for the 868.3 MHz and B IF The nominal bandwidth is 300 kHz for ATA5723 and ATA5724 and 600 kHz for ATA5728. 4.2 Limiting RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is R operated within its linear range, the best S/N ratio is maintained in ASK mode ...
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... Sens Section 14. “Data Interface” on page or GND using a microcontroller. The receiver can be switched S Figure 13-2 on page 30 Steady L State Limited DATA Output Pattern DATA t DATA_min ATA5723/ATA5724/ATA5728 -80 -70 -60 -50 - connected between pin Sens Sens “Data Interface”). ...
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... The BR_Range is defined in the OPMODE register (refer to ing the Receiver” on page The ATA5723/ATA5724/ATA5728 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of V ...
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... When designing the system in terms of receiving bandwidth, the LO deviation must be consid- ered as it also determines the IF center frequency. The total LO deviation is calculated the sum of the deviation of the crystal and the XTO deviation of the ATA5723/ATA5724/ATA5728. Low-cost crystals are specified to be within ±90 ppm over tolerance, temperature, and aging. ...
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... MHz, f XTO for applications using other frequency bands, see table in Clk 5, the frequency of the crystal oscilla- ) which also defines the operating frequency of RFin = 2.069 µs for f = 433.92 MHz. For ATA5723 the Clk RF = 2.0382 µs for f = 315 MHz. Clk RF Transmit = 314.13 MHz, T ...
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... The receiver remains in this state until another value for Sleep is programmed into the OPMODE register. This is particularily useful when several devices share a single data line. (It can also be used for microcontroller polling: using pin POLLING/_ON, the receiver can be switched on and off.) 9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 BR_Range0: BR_Range1: BR_Range2: BR_Range3: ...
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... Bit-check NO Receiving Mode: The receiver is turned on permanently and passes the data stream to the connected microcontroller. It can be set to Sleep mode through an OFF command via Pin DATA or Polling/_ON. Output level on Pin IC_ACTIVE = > high Son ATA5723/ATA5724/ATA5728 12 Sleep: X 1024 T X Sleep Clk Sleep T : Clk T Startup ...
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... Data_out (DATA) T Start-up Start-up mode According to If the edge-to-edge time t bit-check limit T the bit check is terminated and the receiver switches to sleep mode. Figure 8-3. 9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 Bit check ok 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit T Bit-check Start-check mode Figure 8-3, the time window for the bit check is defined by two separate time limits ...
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... CV_Lim reaches Lim_max. This is illustrated in Figure 8-4. Timing Diagram During Bit Check (Lim_min = 14, Lim_max = 24) IC_ACTIVE Bit check Dem_out Bit-check 0 counter T Start-up Start-up mode ATA5723/ATA5724/ATA5728 14 . Using pre-burst patterns that contain various edge-to-edge time ee = Lim_min T XClk = (Lim_max – XClk , T and T . The time resolution defining T ...
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... T Bit-check Bit-check mode Bit-check resulting in a lower current consumption in polling mode. Bit-check , and the count of the checked bits, N requiring a higher value for the transmitter pre-burst T Bit-check Figure 8-2 on page ATA5723/ATA5724/ATA5728 0 T Sleep Sleep mode Lim_max) Bit check failed (CV_Lim Lim_max Sleep Sleep mode varies for each check ...
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... Dem_out Data_out (DATA) Figure 8-8. Debouncing of the Demodulator Output Dem_out Data_out (DATA) t DATA_min ATA5723/ATA5724/ATA5728 16 Figure 8-7 . This clock is also used for the bit-check counter. Data can change its XClk has elapsed. The edge-to-edge time period t XClk . XClk is therefore longer than the maximum time period indicated by the transmitter ...
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... OFF command. Note that the capacitive load at pin DATA is limited (see Sleep Section 14. “Data Interface” on page 9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 Bit-check mode Receiving mode Section 10. “Digital Noise Suppression” on page of the majority of these noise pulses is equal or slightly higher than ee ...
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... Figure 8-11. Timing Diagram of the OFF Command using Pin POLLING/_ON IC_ACTIVE POLLING/_ON Data_out (DATA) Serial bi-directional data line Figure 8-12. Activating the Receiving Mode using Pin POLLING/_ON IC_ACTIVE POLLING/_ON Data_out (DATA) Serial bi-directional data line ATA5723/ATA5724/ATA5728 t10 t7 Bit 1 ("1") (Start Bit) ...
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... ATA5723/ATA5724/ATA5728 “Timing Diagram of the OFF Command using Pin POLLING/_ON” illustrates how to . After the positive edge on pin POLLING/_ON and the delay on2 “ ...
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... POLLING/_ON, the data clock is available if the data clock control logic has detected the dis- tance 2T (Start bit). Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit. Figure 9-1. Data_out (DATA) DATA_CLK Figure 9-2. Data_out (DATA) DATA_CLK ATA5723/ATA5724/ATA5728 20 Timing Diagram of the Data Clock Preburst Bit check ok '1' '1' '1' Dem_out ...
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... Dem_out Receiving mode, bit check active at pin DATA and the external pull-up resistor R L depends additionally on the external voltage V Delay1 and Figure 13-2 on page 30). When the level of Data_In is equal to the level of ATA5723/ATA5724/ATA5728 Data Logical error (Manchester code violation) '0' '1' '1' '?' '0' '0' Data ...
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... Figure 9-5. Figure 9-6. ATA5723/ATA5724/ATA5728 22 Timing Characteristic of the Data Clock (Rising Edge on Pin DATA) Data_Out 0. 0. Serial bi-directional S II data line Data_In DATA_CLK t Delay1 t Delay Timing Characteristic of the Data Clock (Falling Edge of the Pin DATA) Data_Out Serial bi-directional data line Data_In ...
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... Receiving mode, data clock control bit check active logic active Data Receiving mode, Bit-check data clock control mode logic active ATA5723/ATA5724/ATA5728 Figure 10-1 Bit check ok Preburst Data Receiving mode, Receiving mode, data clock control bit check active logic active Bit check ok ...
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... POLLING/_ON must be set to high. This way of suppressing the noise is recommended if the data stream is not Manchester or Bi-phase coded. Figure 10-4. Controlled Noise Suppression Bit check ok Serial bi-directional Preburst data line (DATA_CLK) POLLING/_ON Bit-check mode ATA5723/ATA5724/ATA5728 24 Timing error t < Data stream '1' '1' '1' Dem_out ...
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... Configuring the Receiver The ATA5723/ATA5724/ATA5728 receiver is configured using two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bidirectional DATA port. If the register content has changed due to a voltage drop, this condition is indicated by a the output pattern called reset marker (RM). If this occurs, the receiver must be reprogrammed. ...
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... BR_Range sets the appropriate baud-rate range and simultaneously defines XLim. XLim is used to define the bit-check limits T 11-11 on page Table 11-4. Baud1 Table 11-5. Table 11-6. ATA5723/ATA5724/ATA5728 26 and T Lim_min 28. Effect of the configuration word BR_Range BR_Range Baud0 Baud-rate Range/Extension Factor for Bit-check Limits (XLim) BR_Range0 0 (BR_Range0 = 1 ...
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... Table 11-7. Sleep4 ... 0 ... Table 11-8. Table 11-9. Noise Suppression 9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 Effect of the Configuration Word Sleep Sleep Sleep3 Sleep2 Sleep1 ... ... ... ... ... ... Effect of the Configuration Bit XSleep X Sleep X SleepStd 0 1 Effect of the Configuration Bit Noise Suppression Noise_Disable 0 1 Start Value for Sleep Counter ...
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... Lim_min is also used to determine the margins of the data clock control logic (see Table 11-11. Effect of the Configuration Word Lim_max (1) Lim_max (Lim_max < not applicable) Lim_max5 Lim_max4 Lim_max3 Note: 1. Lim_max is also used to determine the margins of the data clock control logic (see ATA5723/ATA5724/ATA5728 28 Lim_min2 Lim_min1 Lim_min0 Lim_max2 Lim_max1 Lim_max0 1 0 ...
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... Conservation of the Register Information The ATA5723/ATA5724 uses an integrated power-on reset and brown-out detection circuitry as a mechanism to preserve the RAM register information. According to below the threshold voltage V tion registers in that condition. The POR is cancelled after the minimum reset period t exceeds V To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset. ...
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... All 15 bits are programmed this way. The time frame to program a bit is defined by t6. ATA5723/ATA5724/ATA5728 Bit 1 Bit 2 ("0") ("1") (Start bit) (Register select) Programming frame 20V X ATA5723 ATA5724 ATA5728 R pup DATA 0V to 20V Serial bi-directional data line and Figure 13- Bit 14 Bit 15 ("0") ("0") (Poll 8) ...
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... The registers PMODE and LIMIT are set to the default values and the RM is deleted, if present. This t1 values can be used if the connected microcontroller detects an RM. Additionally, this t1 value can generally be used if the receiver operates in default mode. Note that the capacitive load at pin DATA is limited. 9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 31 ...
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... MHz or without SAW Filter 150 SENS DATA IC_ACTIVE POLLING/_ON 3 18 CDEM DGND 17 DATA_CLK 4 16 AVCC MODE 5 ATA5723 TEST1 6 ATA5724 15 RSSI DVCC ATA5728 7 14 AGND XTAL2 8 13 LNAREF XTAL1 9 12 LNA_IN TEST3 10 11 LNAGND TEST2 For 315 MHz application pin MODE must be connected to GND. ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Power dissipation Junction temperature Storage temperature Ambient temperature Maximum input level, input matched to 50 16. Thermal Resistance Parameters Junction ambient 9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 Symbol Min tot –55 stg T – ...
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... Electrical Characteristics ATA5723 All parameters refer to GND –40°C to +105°C, V amb (For typical values 5V 25°C). S amb Test No. Parameter Conditions Symbol 1 Basic Clock Cycle of the Digital Circuitry Basic clock 1.1 T cycle BR_Range0 Extended BR_Range1 1.2 basic clock T BR_Range2 cycle BR_Range3 ...
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... Electrical Characteristics ATA5723 (Continued) All parameters refer to GND –40°C to +105°C, V amb (For typical values 5V 25°C). S amb Test No. Parameter Conditions Symbol Minimum time period between BR_Range = edges at pin DATA BR_Range0 (see Figure BR_Range1 3.3 4-2 and BR_Range2 t DATA_min Figure ...
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... Electrical Characteristics ATA5723 (Continued) All parameters refer to GND –40°C to +105°C, V amb (For typical values 5V 25°C). S amb Test No. Parameter Conditions Symbol 4 Configuration of the Receiver (see Frequency is Frequency of stable within 4.1 the reset after marker POR BR_Range = BR_Range0 Programming BR_Range1 4 ...
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... Sig Sig Sig f 987 IF 1.0 1.8 1.0 1.8 3.2 1.8 3.2 5.6 3.2 5.6 10.0 5.6 ATA5723/ATA5724/ATA5728 = 433.92 MHz and f = 868.3 MHz unless otherwise specified 0 = 868.3 MHz, Variable Oscillator Typ. Max. Min. Typ. 2.066 28/f XTO 16.528 8 T Clk 8.264 4 ...
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... BR_Range = end of a data BR_Range0 8.8 T Pulse stream BR_Range1 (see BR_Range2 Figure 10-3) BR_Range3 *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5723/ATA5724/ATA5728 38 = 4.5V to 5.5V 433.92 MHz and 433.92 MHz f = 868.3 MHz 13.52875 MHz Oscillator 13.55234 MHz Oscillator Min ...
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... ATA5723/ATA5724/ATA5728 = 433.92 MHz and f = 868.3 MHz unless otherwise specified 0 = 868.3 MHz, Variable Oscillator Typ. Max. Min. Typ. 1/ 118.2 (4096 T ) Clk 1624 T Clk 11636 1100 ...
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... Electrical Characteristics ATA5723, ATA5724, ATA5728 All parameters refer to GND –40°C to +105°C, V amb unless otherwise specified. (For typical values: V No. Parameters 11 Current Consumption 11.1 Current consumption 12 LNA, Mixer, Polyphase Low-pass and IF Amplifier (Input Matched According to 12.1 Third-order intercept point 12.2 LO spurious emission 12 ...
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... Electrical Characteristics ATA5723, ATA5724, ATA5728 (Continued) All parameters refer to GND –40°C to +105°C, V amb unless otherwise specified. (For typical values: V No. Parameters Static capacitance at pin 13.6 XTAL1 to GND Static capacitance at pin 13.7 XTAL2 to GND Crystal series resistor Rm at 13.8 start-up ...
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... Electrical Characteristics ATA5723, ATA5724, ATA5728 (Continued) All parameters refer to GND –40°C to +105°C, V amb unless otherwise specified. (For typical values: V No. Parameters Input sensitivity FSK 14.5 300 kHz IF filter (ATA5723/ATA5724) Input sensitivity FSK 14.6 600 kHz IF filter (ATA5728) Sensitivity variation FSK for the full operating range 14 ...
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... Electrical Characteristics ATA5723, ATA5724, ATA5728 (Continued) All parameters refer to GND –40°C to +105°C, V amb unless otherwise specified. (For typical values: V No. Parameters Sensitivity variation FSK for the full operating range 14.8 including IF filter compared 25°C, amb S/N ratio to suppress in-band noise signals ...
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... Electrical Characteristics ATA5723, ATA5724, ATA5728 (Continued) All parameters refer to GND –40°C to +105°C, V amb unless otherwise specified. (For typical values: V No. Parameters 14.18 Reduced sensitivity Reduced sensitivity variation 14.19 over full operating range Reduced sensitivity variation 14.20 for different values of R Sense 14 ...
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... Ordering Information Extended Type Number ATA5723P3-TKQY ATA5724P3-TKQY ATA5728P6-TKQY 21. Package Information 0.25 ±0. Drawing-No.: 6.543-5056.01-4 Issue: 1; 10.03.04 9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 Package SSO20 SSO20 SSO20 6.75 -0.25 0.65 ±0.05 5.85 ±0. Remarks 315 MHz version 433 MHz version 868 MHz version 5.4 ± ...
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