ATA5749-EK1 Atmel, ATA5749-EK1 Datasheet
ATA5749-EK1
Specifications of ATA5749-EK1
Related parts for ATA5749-EK1
ATA5749-EK1 Summary of contents
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... Description ® The Atmel ATA5749 is a fractional-N-PLL transmitter IC for 300MHz to 450MHz operation and is especially targeted for Tire Pressure Sensor Gauges, Remote Keyless Entry, and Passive Entry and other automotive applications. It operates at data rates up to 40kbit/s Manchester for ASK and FSK with a typical 5.5dBm output power at 7 ...
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... Figure 1-1. Block Diagram CLK SDIN_TXDIN SCK ANT2 ANT1 Atmel ATA5749 2 Atmel ATA5749 1 XTO_RDY CLK_DRV 1 XTO Signal Fractional-N-PLL CLK_ON DIV_CNTRL FSK_mod 2 FREQ[0:14] FSEP[0:7] Frac. Digital Control and 433_N315 Registers 3 ASK_mod PFD PWR[0: VCO 10 EN Power up/down 9 GND Div XTO1 LP XTO (FOX) ...
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... SDIN_TXDIN 2 Atmel ATA5749 SCK 3 ANT2 4 ANT1 5 Function CLK output Serial bus data input and TX data input Serial bus clock input Antenna interface Antenna interface Crystal/C connection LOAD2 Crystal/C connection LOAD1 Supply input Supply GND Enable input Atmel ATA5749 GND XTO1 6 XTO2 3 ...
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... FSEP[0:7] = 100 and S434_N315 = 0. By setting FREQ[0:14] = 14342, FSEP[0:7] = 100 and S434_N315 = 1, 433.92MHz can be realized. Atmel ATA5749 4 ® ATA5749 block diagram is shown in Table 3-1. Note that in the case Output Parameter Formulas S434_N315 = LOW (24 + (FREQ + 0.5)/16384) (24 + (FREQ + FSEP + 0.5)/16384) ...
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... HIGH switch on the upper FSK-frequency. 9128G–RKE–03/11 Class C Power Amplifier Output V ANT1 ANT2 I = (PWR[0:3]) Pulse ANT1 L1 Power Meter ANT1 LOPT ANT2 is calibrated during Atmel Pulse Atmel ATA5749 5 I ANT2 4 ® ATA5749 production to can be programmed with the 4-bit value in Pulse Figure 3-1. 5 ...
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... XTO_RDY signal so that the first period of the CLK output is always a full period (no CLK output spike at activation). To lower overall current consumption possible to power down the entire chip except for the crystal oscillator block. This can be achieved when the CLK_ONLY is “set”. Atmel ATA5749 6 2.5mm crystals). Figure 1-1 on page 2 > ...
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... FREQ[0:14] FSEP[0:7] Digital Control and 433_N315 Registers 3 ASK_mod SCK PWR[0: shows the typical application circuit. For C6, the supply-voltage blocking capacitor, 20pF NPO capacitors. C1 (typically 1nF X7R) is needed for the Atmel ATA5749 10 EN Power up/down 9 GND Frac. Div. 8 PFD XTO1 LP XTO (FOX) ...
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... ATA5749 ANT1, ANT2 into the matching network. This is is the circuit that was used to obtain the typical output power measurements in and typical current consumption in provide recommended values and performance info at various output is defined as the impedance seen from the Atmel ATA5749 LOPT Output Power Measurement Circuit Power Meter ...
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... Atmel ATA5749 are Cpar LOPT LOPT ( ) ( ) (pF) 2950 110 + 540j 0.9 1940 150 + 520j 0.9 1550 190 + 520j 0.9 1250 220 + 480j 0.9 1000 240 + 430j 0.9 730 280 + 360j 0.9 580 290 + 300j 0 ...
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... Figure 4-3. Figure 4-4. Atmel ATA5749 10 Typical Measured Output Power -40 27 Temperature [ Typical Current Consumption I at Port - 3.6V, PWR[0:15] = 15] = 3.0V, PWR[0:15 1.9V, PWR[0:15 3.6V, PWR[0:15 3.0V, PWR[0:15 1.9V, PWR[0:15 ° = 3.6V, P WR[0:15 3.0V, P WR[0:15 1.9V, P WR[0:15 3.6V, P WR[0:15 3.0V, P WR[0:15 1.9V, P WR[0:15 ...
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... The switching effect on VCO frequency in ASK Mode is very low if a correct PCB layout and decoupling is used. Therefore, power ramping is not needed to achieve a clean spectrum (see Figure Figure 5-1. 9128G–RKE–03/11 5-1). Typical RF Spectrum of 40kHz ASK Modulation at Pout = 12.5dBm Atmel ATA5749 11 ...
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... FREQ FSEP FSEP FSEP FSEP [0] [7] [6] [5] [4] FSK Shift = FSEP[0..7] FSEP[0] + ... + FSEP[7] Table 6-2. Name CLK_ONLY S434_N315 FREQ[0:14] FSEP[0:7] DIV_CNTRL PWR[0:3] ASK_NFSK CLK_ON Atmel ATA5749 12 Table 6 FREQ FREQ FREQ FREQ [11] [10] [9] [8] Frequency Adjust = FREQ[0..14] FREQ[ FREQ[ FREQ[2] + ... + FREQ[14 FSEP ...
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... T SCK_High T SCK_Cycle T SCK_Low T Hold MSB X MSB-1 shows the situation when the programming terminates faster then the XTO is ready. T XTO 32-bit Configuration Start_Up_ Mode_2 Atmel ATA5749 Figure 6-1. Note that the maximum T SDIN_TXDIN_setup X XTO TX-Data PLL FSK; TX_Mode2 TX_ OFF_Mode ASK: ...
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... SPI bus as shown in After data transmission, the device can be switched back to OFF_Mode by asserting EN, SCK, and SDIN_TXDIN to a LOW state. An example of programming from the Reset_Register_Mode is shown in Atmel ATA5749 14 shows the combination with slow programming and a faster ramp up of XTO. A Table 6-3 on page ...
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... Power up/down; XTO; digital control; fractional-N-PLL; CLK_DRV Power up/down; XTO; digital control; CLK_DRV Power up/down; XTO; digital control; CLK_DRV Power up/down; XTO; digital control; CLK_DRV Power up/down; XTO; digital control; CLK_DRV 1. Only if activated with CLK_ON = HIGH Atmel ATA5749 T PLL 32-bit TX_ Configuration Data FSK ...
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... XTO cycles (T PLL register programmed and XTO_RDY = 'High' To transition from one state to another, only the conditions next to the transition arrows must be fulfilled. No additional settings are required. Atmel ATA5749 'High' SDIN_TXDIN = 'Low 'Low' SDIN_TXDIN = 'Low' CLK_Only = 'Low' register parity programmed ...
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... ESD Protection Circuit CLK SCK EN Symbol tot stg Tamb1 < 0.25V or Tamb2 < 0.25V HBM HBM MM MM CDM Symbol R thJA Atmel ATA5749 ANT1 ANT2 XTO2 XTO1 Min. Max. –0.3 +4.0 100 150 –55 +125 –40 +125 175 –4 +4 –2 +2 –200 +200 –150 +150 750 ...
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... TX_Mode2 Table 4-1 on page 9 Table 4-2 on page 9 *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: (Pin Number) in brackets mean they are measured matched to 50 according to and optimum load impedances according to Atmel ATA5749 18 = 3.0V and T S Pin +25° +85° ...
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... LOPT and –40°C to +125° (5) OUT_x OUT 9pF < 2.0pF 0 = 9pF 6, 7 < 10fF M Table 4-1 and Table 4-2 on page 9 Atmel ATA5749 = 13.0000MHz, XTO = 25°C amb Symbol Min. Typ. Max. I 5.4 6.7 S_P1 I 7.0 S_P1 P 4.0 5.5 7.0 OUT_2 I 7.3 8.8 ...
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... Out of Loop Phase At 1MHz 4.5 noise (VCO) At 36MHz *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: (Pin Number) in brackets mean they are measured matched to 50 according to and optimum load impedances according to Atmel ATA5749 20 = 3.0V and T S Pin < 10pF LOAD = 13 ...
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... XTO ± XTO ±f XTO ± XTO ± f XTO 5 ± f XTO 5 5 XTO XTO Table 4-1 and Table 4-2 on page 9 Atmel ATA5749 = 13.0000MHz, XTO = 25°C amb Symbol Min. Typ. Max MOD_FSK MOD_ASK –47 Spur –47 –60 Spur –47 –58 Spur – ...
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... Timing Characteristics (Atmel ATA5749 1.9V to 3.6V –40°C to +125°C. Typical values are given amb (pin 9). Parameters where crystal relevant parameters are important correspond to a crystal with C and R 170 unless otherwise specified. M No. Parameters Test Conditions EN set-up time to rising 1.1 edge of SCK SDIN_TXDIN set-up time 1 ...
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... Type means 100% tested 100% correlation tested Characterized on samples Design parameter 9128G–RKE–03/11 = 3.0V and T S Pin Symbol Min. Typ – 0. 160 250 PDN – 0. 160 250 PDN – 0. 160 250 PDN Atmel ATA5749 = 25°C, all inputs are amb Max. Unit Type* 0. 380 k 0. 380 k 0. 380 k 23 ...
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... Ordering Information Extended Type Number ATA5749-6DQ ATA5749C-6DQ 14. Package Information Package: TSSOP 10 (acc. to JEDEC Standard MO-187) Dimensions in mm Not indicated tolerances ± 0.05 0.5 nom 0 nom. Atmel ATA5749 24 Package TSSOP10 TSSOP10 3 ±0.1 0. Remarks - - 3 ±0.1 3.8 ±0.3 4.9 ±0.1 technical drawings according to DIN specifications Drawing-No ...
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... History ATA5749C on page 1 added Section 13 “Ordering Information” on page 24 changed Page 9: Table 4-1 changed Page 9: Table 4-2 changed El. Char. table: rows 1.2, 1.3, 1.4, 1.7, 1.8, 1.9, 2.1, 2.2, 2.4, 2.5 changed Dig. Port Char. table: row 1.3 changed ...
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