MAX1471EVKIT-433 Maxim Integrated Products, MAX1471EVKIT-433 Datasheet - Page 18

• Manufacturer Part Number: MAX1471EVKIT-433
• Description: EVAL KIT FOR MAX1471 433MHZ
• Manufacturer: Maxim Integrated Products
• Type: Receiver, ASK/FSKr

Specifications of MAX1471EVKIT-433

• Frequency: 433MHz
• For Use With/related Products: MAX1471 ~ 433 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For example, if data is being received at 315MHz, the
crystal frequency is 9.509375MHz. Dividing the crystal
frequency by 100kHz and rounding to the nearest inte-
ger gives 95, or 0x5F hex. So for 315MHz, 0x5F would
be written to the oscillator frequency register.
The AGC dwell timer holds the AGC in low-gain state
for a set amount of time after the power level drops
below the AGC switching threshold. After that set
amount of time, if the power level is still below the AGC
threshold, the LNA goes into high-gain state. This is
important for ASK since the modulated data may have
a high level above the threshold and a low level below
the threshold, which without the dwell timer would
cause the AGC to switch on every bit.
The AGC dwell time is dependent on the crystal fre-
quency and the bit settings of the AGC dwell timer reg-
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Figure 11. Read Command in 3-Wire Interface
Table 3. Command Bits
18
SCLK
SCLK
DIO
DIO
CS
CS
______________________________________________________________________________________
0
0
0x4–0xF
C[3:0]
AGC Dwell Timer Register (Address: 0xA)
0x0
0x1
0x2
0x3
COMMAND
COMMAND
0
0
READ
READ
1
1
0
0
A3
A3
A2
A2
ADDRESS
ADDRESS
A1
A1
A0
A0
DESCRIPTION
No operation
Master reset
Read data
Write data
Not used
0
0
0
0
0
0
0
0
DATA
DATA
0
0
0
0
ister. To calculate the dwell time, use the following
equation:
where Reg 0xA is the value of register 0xA in decimal.
To calculate the value to write to register 0xA, use the
following equation and use the next integer higher than
the calculated result:
For Manchester Code (50% duty cycle), set the dwell
time to at least twice the bit period. For nonreturn-to-
zero (NRZ) data, set the dwell to greater than the peri-
od of the longest string of zeros or ones. For example,
using Manchester code at 315MHz (f
9.509375MHz) with a data rate of 4kbps (bit period =
125µs), the dwell time needs to be greater than 250µs:
Choose the register value to be the next integer value
higher than 11.14, which is 12 or 0x0C hex.
The default value of the AGC dwell timer on power-up
or reset is 0x0D.
Reg 0xA ≥ 3.3 x log
0
0
0
0
Reg 0xA ≥ 3.3 x log
R7
R7
R6
R6
D
R5
R5
well Time
10
REGISTER DATA
REGISTER DATA
8 BITS OF DATA
R4
R4
(250µs x 9.509375MHz) ≈11.14
R3
R3
16 BITS OF DATA
10
=
(Dwell Time x f
R2
R2
2
f
Reg0xA
XTAL
R1
R1
R0
A3
R7
REGISTER
XTAL
DATA
XTAL
)
R0
=