MAX1471EVKIT-433 Maxim Integrated Products, MAX1471EVKIT-433 Datasheet - Page 19

• Manufacturer Part Number: MAX1471EVKIT-433
• Description: EVAL KIT FOR MAX1471 433MHZ
• Manufacturer: Maxim Integrated Products
• Type: Receiver, ASK/FSKr

Specifications of MAX1471EVKIT-433

• Frequency: 433MHz
• For Use With/related Products: MAX1471 ~ 433 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4. Register Summary
The MAX1471 must be calibrated to ensure accurate
timing of the off timer in discontinuous receive mode or
when receiving FSK signals. The first step in calibration
is ensuring that the oscillator frequency register
(address: 0x3) has been programmed with the correct
divisor value (see the Oscillator Frequency Register
section). Next, enable the mixer to turn the crystal dri-
ver on.
Calibrate the polling timer by setting POL_CAL_EN = 1
in the configuration register (register 0x1). Upon com-
pletion, the POL_CAL_DONE bit in the status register
(register 0x8) is 1, and the POL_CAL_EN bit is reset to
zero. If using the MAX1471 in continuous receive
mode, polling timer calibration is not needed.
FSK receiver calibration is a two-step process. Set
FSKCALLSB = 1 (register 0x1) or to reduce the calibra-
tion time, accuracy can be sacrificed by setting the
FSKCALLSB = 0. Next, initiate FSK receiver calibration,
set FSK_CAL_EN = 1. Upon completion, the
REGISTER
A[3:0]
0xA
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
CPU recovery timer—t
Status register (read only)
______________________________________________________________________________________
Power configuration
Oscillator frequency
RF settle timer—t
RF settle timer—t
REGISTER NAME
AGC dwell timer
Off timer—t
Off timer—t
Configuration
(upper byte)
(upper byte)
(lower byte)
(lower byte)
Control
ASK/FSK Superheterodyne Receiver
OFF
OFF
315MHz/434MHz Low-Power, 3V/5V
RF
RF
CPU
Enables/disables the LNA, AGC, mixer, baseband, peak detectors, and sleep mode
(see Table 6).
Sets options for the device such as output enables, off-timer prescale, and
discontinuous receive mode (see Table 7).
Controls AGC lock, peak-detector tracking, as well as polling timer and FSK
calibration (see Table 8).
Sets the internal clock frequency divisor. This register must be set to the integer
result of f
Sets the duration that the MAX1471 remains in low-power mode when DRX is active
(see Table 10).
Increases maximum time the MAX1471 stays in lower power mode while CPU wakes
up when DRX is active (see Table 11).
During the time set by the settle timer, the MAX1471 is powered on with the peak
detectors and the data outputs disabled to allow time for the RF section to settle.
DIO must be driven low at any time during t
restarts (see Table 12).
Provides status for PLL lock, AGC state, crystal operation, polling timer, and FSK
calibration (see Table 9).
Controls the dwell (release) time of the AGC.
Calibration
XTAL
/100kHz (see the Oscillator Frequency Register section).
FSK_CAL_DONE bit in the status register (register 0x8)
is one, and the FSK_CAL_EN bit is reset to zero.
When in continuous receive mode and receiving FSK
data, recalibrate the FSK receiver after a significant
change in temperature or supply voltage. When in dis-
continuous receive mode, the polling timer and FSK
receiver (if enabled) are automatically calibrated during
every wake-up cycle.
The first timer, t
that is configured using: register 0x4 for the upper byte,
register 0x5 for the lower byte, and bits PRESCALE1
and PRESCALE0 in the configuration register (register
0x1). Table 10 summarizes the configuration of the t
timer. The PRESCALE1 and PRESCALE2 bits set the
size of the shortest time possible (t
data written to the t
plied by the time base to give the total t
power-up, the off timer registers are set to zero and
must be written before using DRX mode.
DESCRIPTION
OFF
LOW
OFF
(see Figure 12), is a 16-bit timer
= t
registers (0x4 and 0x5) is multi-
CPU
+ t
RF
or the timer sequence
OFF
Off Timer (t
time base). The
OFF
time. On
OFF
OFF
19
)