MAX1471EVSYS-433 Maxim Integrated Products, MAX1471EVSYS-433 Datasheet - Page 17

• Manufacturer Part Number: MAX1471EVSYS-433
• Description: EVAL KIT FOR MAX1471 433MHZ
• Manufacturer: Maxim Integrated Products
• Type: Receiver, ASK/FSKr

Specifications of MAX1471EVSYS-433

• Frequency: 433MHz
• For Use With/related Products: MAX1471 ~ 433 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 9. Data Input Diagram
Figure 10. Read Command on a 4-Wire SERIAL Interface
In the discontinuous receive mode (DRX = 1), the
power signals of the different modules of the MAX1471
toggle between OFF and ON, according to internal
timers t
the frequency divisor of the external crystal in the oscil-
lator frequency register (register 0x3). This number is
the integer result of f
discontinuous receive mode for the first time, it is also
necessary to calibrate the timers (see the Calibration
section).
The MAX1471 uses a series of internal timers (t
t
sequence begins when both CS and DIO are one. The
MAX1471 has an internal pullup on the DIO pin, so the
user must tri-state the DIO line when CS goes high.
CPU
ADATA (IF DOUT_ASK = 1)
FDATA (IF DOUT_FSK = 1)
SCLK
, and t
DIO
CS
OFF
SCLK
, t
0
DIO
CS
RF
CPU
Discontinuous Receive Mode (DRX = 1)
COMMAND
0
) to control its power-up. The timer
READ
, and t
______________________________________________________________________________________
1
C3
XTAL
0
RF
C2
COMMAND
A3
/100kHz. Before entering the
. It is also necessary to write
ASK/FSK Superheterodyne Receiver
C1
A2
ADDRESS
315MHz/434MHz Low-Power, 3V/5V
A1
C0
A0
A3
0
0
A2
ADDRESS
0
A1
OFF
0
DATA
A0
,
0
0
D7
The external CPU can then go to a sleep mode during
t
DIO serves as the wake-up signal for the CPU, which
must then start its wake-up procedure, and drive DIO
low before t
the MAX1471 enables the FSKOUT and/or ASKOUT
data outputs. The CPU must then keep DIO low for as
long as it may need to analyze any received data.
Releasing DIO causes the MAX1471 to pull up DIO,
reinitiating the t
The MAX1471 has an internal frequency divider that
divides down the crystal frequency to 100kHz. The
MAX1471 uses the 100kHz clock signal when calibrating
itself and also to set the image-rejection frequency. The
hexadecimal value written to the oscillator frequency reg-
ister is the nearest integer result of f
OFF
0
D6
. A high-to-low transition on DIO, or a low level on
0
Oscillator Frequency Register (Address: 0x3)
D5
C3
R7
R7
LOW
COMMAND
D4
C2
R6
R6
OFF
DATA
expires (t
R5
C1
R5
D3
timer.
REGISTER DATA
REGISTER DATA
C0
R4
R4
D2
A3
R3
R3
CPU
ADDRESS
D1
R2
A2
R2
+ t
A1
R1
R1
RF
D0
XTAL
). Once t
A0
R0
R0
/100kHz.
D7
R7
R7
REGISTER
REGISTER
DATA
DATA
DATA
RF
D0
R0
R0
expires,
17