MAX1471EVSYS-433 Maxim Integrated Products, MAX1471EVSYS-433 Datasheet - Page 20

• Manufacturer Part Number: MAX1471EVSYS-433
• Description: EVAL KIT FOR MAX1471 433MHZ
• Manufacturer: Maxim Integrated Products
• Type: Receiver, ASK/FSKr

Specifications of MAX1471EVSYS-433

• Frequency: 433MHz
• For Use With/related Products: MAX1471 ~ 433 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

During t
supply current (5.0µA typ), where all of its modules are
turned off, except for the t
pletion of the t
by asserting DIO low.
The second timer, t
the power-up of the MAX1471, thereby providing extra
power savings and giving a CPU the time required to
complete its own power-on sequence. The CPU is sig-
naled to begin powering up when the DIO line is pulled
low by the MAX1471 at the end of t
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Table 5. Register Configuration
* Power-up state = 1. All other bits, power-up state = 0.
20
POWER CONFIGURATION (0x0)
CONFIGURATION (0x1)
CONTROL (0x2)
OSCILLATOR FREQUENCY (0x3)
OFF TIMER (upper byte) (0x4)
OFF TIMER (lower byte) (0x5)
CPU RECOVERY TIMER (0x6)
RF SETTLE TIMER (upper byte) (0x7)
RF SETTLE TIMER (lower byte) (0x8)
STATUS REGISTER (read only) (0x9)
AGC DWELL TIMER (0xA)
______________________________________________________________________________________
OFF
, the MAX1471 is operating with very low
A3 A2 A1 A0
ADDRESS
OFF
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
CPU
time, the MAX1471 signals the user
(see Figure 12), is used to delay
CPU Recovery Timer (t
OFF
timer itself. Upon com-
OFF
LNA_EN
. t
LOCK
DET
t15
t15
CPU
D7
d7
t7
t7
t7
X
X
X
then begins
AGC_EN
AGCST
LOCK
GAIN
SET*
AGC
t14
t14
D6
d6
t6
t6
t6
X
CPU
)
FSKCALL
MIXER_
ALIVE
CLK
t13
t13
D5
EN
SB
d5
t5
t5
t5
X
X
counting down, while DIO is held low by the MAX1471.
At the end of t
t
The possible t
The data written to the t
by 120µs to give the total t
CPU timer register is set to zero and must be written
before using DRX mode.
The third timer, t
RF sections of the MAX1471 to power up and stabilize
before ASK or FSK data is received. t
CPU
is an 8-bit timer, configured through register 0x6.
FSKBB_
DOUT
FSK_
t12
t12
dt4
D4
EN
d4
t4
t4
t4
X
X
DATA
CPU
CPU
FSKTRK_
RF
FSKPD_
, the t
DOUT
ASK_
settings are summarized in Table 11.
dt3*
EN
EN
t11
t11
D3
d3
(see Figure 12), is used to allow the
t3
t3
t3
X
RF
CPU
counter begins.
ASKBB_
ASKTRK_
CPU
TOFF_
PS1
dt2*
EN
EN
t10
t10
register (0x6) is multiplied
D2
d2
t2
t2
t2
X
time. On power-up, the
RF Settle Timer (t
ASKPD_
P OL_C AL
C AL_E N
_D O N E
TOFF_
P OL_
RF
PS0
EN
dt1
D1
d1
t9
t1
t1
t9
t1
begins count-
FSK_CAL
FSK_CAL
_DONE
SLEEP
MODE
DRX_
_EN
dt0*
D0
d0
t8
t0
t0
t8
t0
RF
)