TDA7580 STMicroelectronics, TDA7580 Datasheet - Page 31

• Manufacturer Part Number: TDA7580
• Description: IC PROC FM/AM IF SAMPLING 64LQFP
• Manufacturer: STMicroelectronics

Specifications of TDA7580

• Function: FM/AM Processor
• Frequency: 10.7MHz Center
• Rf Type: AM, FM
• Secondary Attributes: On-Chip A/D Converter
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TDA7580
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system is the shift register and the read data buffer. The system is single buffered in the
transfer direction and double buffered in the receive direction.
High speed serial synchronous interface (HS
The high speed serial synchronous interface is a module to send and receive data at high
rate (up to 9.25Mbit/s per channel) in order to exchange data between 2 separate TDA7580
chip.
The exchanged data are related to signals that are used to increase reception quality in car
radio systems, which make use of antenna diversity based upon two separate antenna and
tuner sections.
The channel synchronization clock has a programmable duty cycle, so to reduce in band
harmonics noise.
Tuner AGC keying DAC (KEYDAC)
This DAC provides the front-end tuner with an analogue signal to be used to control the
automatic gain controlled stage, thus giving all time the best voltage dynamic range at the
IFADC input.
Asynchronous sample rate converter (ASRC)
This hardware module provides a very flexible way to adapt the internal audio rate, to the
one of an external source. It does not require further work off the DSP.
There is no need to explicitly configure the input and the output sample rates, as the ASRC
solves this problem with an automatic digital ratio locked loop.
Main features are:
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IF band pass
The IFADC is a band pass Sigma Delta A to D converter with sampling rate of 37.05MHz
(nominal) and notch frequency of 10.7MHz. The structure is a second order switched
capacitor multi bit modulator with self calibration algorithm to adjust the notch frequency.
The differential ended input allows 4.0Vpp voltage dynamic range, and reduces the inferred
noise back to the previous stage (tuner), and in turn gives high rejection to common mode
noises.
The high linearity (very high IMD) is needed to fulfill good response of the channel
equalization algorithm.
Low thermal and 1/f noise assures high dynamic range.
Automatic tracking of sample frequency
Fully digital ratio locked loop
Sampling clock jitter rejection
Up conversion up to 1:2 Ratio
Linear phase
Σ Δ
analogue to digital converter (IFADC)
Functional description
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