AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet
AD6636CBCZ
Specifications of AD6636CBCZ
Available stocks
Related parts for AD6636CBCZ
AD6636CBCZ Summary of contents
Page 1
FEATURES 4/6 independent wideband processing channels Processes 6 wideband carriers (UMTS, CDMA2000) 4 single-ended or 2 LVDS parallel input ports (16 linear bit plus 3-bit exponent) running at 150 MHz Supports 300 MSPS input using external interface logic Three 16-bit ...
Page 2
AD6636 TABLE OF CONTENTS General Description ......................................................................... 4 Specifications..................................................................................... 6 Recommended Operating Conditions ...................................... 6 Electrical Characteristics............................................................. 6 , General Timing Characteristics ................................................ 7 , Microport Timing Characteristics ............................................ Serial Port Timing Characteristics ........................................... 9 Explanation of ...
Page 3
REVISION HISTORY 6/05—Rev Rev. A Changes to Format ............................................................. Universal Changes to Figure 1...........................................................................1 Changes to Applications...................................................................1 Changes to General Description .....................................................4 Changes to Table 3 ............................................................................7 Changes to Table 5 ............................................................................9 Changes to Table 8 ..........................................................................11 Changes ...
Page 4
AD6636 GENERAL DESCRIPTION The AD6636 is a digital downconverter intended for IF sampling or oversampled baseband radios requiring wide bandwidth input signals. The AD6636 has been optimized for the demanding filtering requirements of wideband standards, such as CDMA2000, UMTS, and ...
Page 5
The overall filter response for the AD6636 is the composite of all the combined filter stages. Each successive filter stage is capable of narrower transition bandwidths but requires a greater number of CLK cycles to calculate the output. More decimation ...
Page 6
AD6636 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Table 1. Parameter VDDCORE VDDIO T AMBIENT ELECTRICAL CHARACTERISTICS Table 2. Parameter LOGIC INPUTS (NOT 5 V TOLERANT) Logic Compatibility Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance LOGIC ...
Page 7
GENERAL TIMING CHARACTERISTICS Table 3. Parameter CLK TIMING REQUIREMENTS t CLKx Period ( CLK t CLKx Width Low ( CLKL t CLKx Width High ( ...
Page 8
AD6636 MICROPORT TIMING CHARACTERISTICS Table 4. Parameter MICROPORT CLOCK TIMING REQUIREMENTS t CPUCLK Period CPUCLK t CPUCLK Low Time CPUCLKL t CPUCLK High Time CPUCLKH INM MODE WRITE TIMING (MODE = 0) to ↑CPUCLK Setup Time t 3 Control SC ...
Page 9
SERIAL PORT TIMING CHARACTERISTICS Table 5. Parameter SERIAL PORT CLOCK TIMING REQUIREMENTS t SCLK Period SCLK t SCLK Low Time SCLKL t SCLK High Time SCLKH SPI PORT CONTROL TIMING REQUIREMENTS (MODE = 0) SDI to ↑SCLK Setup Time t ...
Page 10
AD6636 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Rating ELECTRICAL VDDCORE Supply Voltage 2.2 V (Core Supply) VDDIO Supply Voltage 4.0 V (Ring or IO Supply) Input Voltage −0.3 to +3.6 V (Not 5 V Tolerant) Output Voltage −0.3 to VDDIO ...
Page 11
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND INC3 IND4 IND7 CLKD B IND0 VDDIO INC2 IND5 IND6 C EXPA1 EXPD1 INC0 INC1 IND3 D EXPB0 EXPC2 EXPC1 EXPD0 IND2 LVDS_ E INA14 INA15 EXPA0 GND ...
Page 12
AD6636 Mnemonic Type Pin No. EXPB[0:2] Bidirectional D1, F3, G4 EXPC[0:2] Bidirectional F4, D3, D2 EXPD[0:2] Bidirectional D4, C2, F5 CLKA, CLKB Input K1, L1 CLKC, CLKD Input A6, A5 INA[0:15], LVDS Input See Table 9 INB[0:15] INC[0:15], LVDS Input ...
Page 13
Mnemonic Type Pin No. SERIAL PORT CONTROL SCLK Input R1 SDO 1 Output M6 2 SDI Input N11 STFS Input N4 SRFS Input P4 SCS Input N5 MSB_FIRST Input R3 SMODE Input P5 JTAG 1 TRST Input B13 2 TCLK ...
Page 14
AD6636 TIMING DIAGRAMS RESET CLKx CLKA t CLKx CPUCLK SCLK CLKA SYNC [3:0] t RESL Figure 3. Reset Timing Requirements t CLKH t CLKL Figure 4. CLK Switching Characteristics ( for Individual Input Ports) t ...
Page 15
CLKx EXPx[2:0] Figure 9. Gain Control Word Output Switching Characteristics CLKx INx[15:0] EXPx[15:0] PCLK t SPA PxACK t DPREQ PxREQ t DPP Px [15:0] PxIQ PxCH [2:0] PxGAIN Figure 11. Master Mode PxACK to PCLK Switching Characteristics t CLK t ...
Page 16
AD6636 PCLK PxACK t DPREQ PxREQ Px [15:0] t PxIQ DPIQ PxCH [2:0] PxGAIN CPUCLK SAM A [7:0] t SAM D [15:0] RDY NOTE: t ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ...
Page 17
CPUCLK SAM A [7:0] VALID ADDRESS D [15:0] t DRDY RDY t ACC NOTE: t ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM CPUCLK CYCLES. ACC ...
Page 18
AD6636 CPUCLK R SAM A [7:0] D [15:0] DTACK NOTE: t ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM CPUCLK CYCLES. ACC SCLK t SSCS ...
Page 19
SCLK t SSCS SCS SMODE SDO t HSTFS t SSTFS STFS MODE SCLK t SSCS SCS SMODE t HSDI t SSDI SDI D0 MODE SCLK t SSCS SCS SMODE t DSDO SDO D0 MODE LOGIC 1 t DSDO D0 D1 ...
Page 20
AD6636 THEORY OF OPERATION ADC INPUT PORT The AD6636 features four identical, independent high speed ADC input ports named and D. These input ports have the flexibility to allow independent inputs, diversity inputs, or complex I/Q inputs. ...
Page 21
D13 (MSB) IN15 AD6645 14-BIT ADC AD6636 D0 (LSB) IN2 IN1 IN0 GAIN RANGING CONTROL EXP2 BITS OR GROUNDED EXP1 EXPONENT BITS EXP0 Figure 23. Typical Interconnection of the AD6645 Fixed-Point ADC and AD6636 Scaling with Floating-Point ADC An example ...
Page 22
AD6636 The PLL clock multiplier is programmable and uses input clock rates between 4 MHz and 150 MHz to give a system clock rate (output high as 200 MHz. The output clock rate is given by × CLKA ...
Page 23
A programmable pipeline delay given by the 6-bit value (maximum delay of 63 clock cycles) is placed between the gain control output and the EXP[2:0] input. Therefore, the external gain-ranging block’s settling delays ...
Page 24
AD6636 Figure block diagram of the peak detector logic. The MSR contains the absolute magnitude of the peak detected by the peak detector logic. FROM MEMORY MAP POWER MONITOR DOWN IS COUNT = 1? PERIOD REGISTER COUNTER ...
Page 25
Additional Control Bits For additional flexibility in the power monitoring process, two control bits are provided in the power-monitor control register. They are the disable monitor period timer bit and the clear-on- read bit. These options have the same function ...
Page 26
AD6636 Table 12. Correction Control Registers Register Bits Description I/Q Correction Control Amplitude Loop Phase Loop Loop BW 3 Reserved (Logic 0) 2 Amplitude Correction Enable 1 Phase ...
Page 27
MAG(I)) can be between 1.125 and 0.875 with a 14-bit resolution. When the amplitude offset correction circuit is disabled, the value in the amplitude offset correction register is multiplied by the Q path data and added to the Q path ...
Page 28
AD6636 SIGNAL OF INTEREST IMAGE –fs/2 –7fs/16 –3fs/8 –5fs/16 –fs/4 AFTER FREQUENCY TRANSLATION –fs/2 –7fs/16 –3fs/8 –5fs/16 –fs/4 FREQUENCY TRANSLATION (SINGLE 1MHz CHANNEL TUNED TO BASEBAND) For example, if the carrier frequency is 100 MHz and the clock frequency is ...
Page 29
If a low noise floor is desired and the higher spurs can be tolerated or filtered by subsequent stages, then phase dither is not needed. Amplitude Dither This can be used to ...
Page 30
AD6636 CIC Rejection Table 14 illustrates the amount of bandwidth as a percentage of the data rate into the CIC stage, which can be protected with various decimation rates and alias rejection specifications. The maximum input rate into the CIC ...
Page 31
This filter runs at the same sample rate as the CIC filter output rate and is given FIR1 in CIC where the input rate in to the channel the decimation ...
Page 32
AD6636 6-Tap Fixed Coefficient Filter (FIR2) Following the first cascade of the FIR1 and HB1 filters is the second cascade of the FIR2 and HB2 filters. The 6-tap, fixed- coefficient FIR2 filter is useful in providing extra alias protection for ...
Page 33
FRACTION OF HB2 INPUT SAMPLE RATE Figure 35. HB2 Filter Response to the Input Rate of the Filter ...
Page 34
AD6636 coefficient memory registers for individual channels. The input and output data to the block are both 20 bit. Symmetry Though the MRCF filter does not require symmetrical filters, if the filter is symmetrical, the symmetry bit in the MRCF ...
Page 35
Coefficient Offset More than one set of filter coefficients can be loaded into the coefficient RAM at any given time (given sufficient RAM space). The coefficient offset can be used in this case to access the two or more different ...
Page 36
AD6636 5. Write the stop address for the coefficient RAM, typically equal to ceil(NTAPS/2) – the DRCF stop address register. 6. Write all coefficients to the DRCF coefficient memory register, starting with the middle of the filter and ...
Page 37
Maximum Number of Taps Calculated The output rate of the CRCF filter is given DRCF f CRCF M CRCF where the data rate out of the DRCF filter and into the CRCF DRCF filter. M ...
Page 38
AD6636 INTERPOLATING HALF-BAND FILTER The AD6636 has interpolating half-band FIR filters that immediately follow the CRCF programmable FIR filters and precede the second data router. Each interpolating half-band filter takes 22-bit I and 22-bit Q data from the preceding CRCF ...
Page 39
CH0 CH1 CH2 CH3 CH4 CH5 The interleaving function is a simple time-multiplexing function, with a lower data rate on the input side and a higher data rate on the output side. The output data rate is the sum of ...
Page 40
AD6636 Table 24. Definitions for Complex Control Register Selections Complex Control Word Data Routing 000 No complex filters 001 Stream 0/Stream 1 combined 010 Stream 0/Stream 1 combined, Stream 2/Stream 3 combined 011 Stream 0/Stream 1 combined, Stream 2/Stream 3 ...
Page 41
I 22 BITS Q POWER × – × z Three sources of error can be introduced by the AGC function: underflow, overflow, and modulation. Underflow is caused by truncation of bits below ...
Page 42
AD6636 The average and decimate operations are tied together and implemented using a first-order CIC filter and FIFO registers. Gain and bit growth are associated with CIC filters and depend on the decimation ratio. To compensate for the gain associated ...
Page 43
The open-loop gain used in the second-order loop G(z) is given by one of the following equations: If Error < Error Threshold Error > Error Threshold The open-loop transfer function for ...
Page 44
AD6636 clipping level option provides a way to prevent truncating those signals and still provide an AGC that attacks quickly and settles to the desired output level. The signal path for this mode of operation is shown with dotted lines ...
Page 45
Interleaved I/Q Mode Parallel port channel mode is selected by writing 0 to the data format bit for the parallel port in consideration. In this mode, I and Q words from the AGC are output on the same 16-bit data ...
Page 46
AD6636 Parallel IQ Mode In this mode, eight bits of I data and eight bits of Q data are output on the data bus simultaneously during one PCLK cycle. The I byte is the most significant byte of the port, ...
Page 47
In Figure 42, the PxACK is already pulled high and, therefore, the 8-bit I data and 8-bit Q data are simultaneously output on the data bus on the next PCLK rising edge after PxREQ is driven logic high. The PxIQ ...
Page 48
AD6636 USER-CONFIGURABLE, BUILT-IN SELF-TEST (BIST) Each channel of AD6636 includes a BIST block. The BIST, along with an internal test signal (pseudorandom test input signal), can be used to generate a signature. This signature can be compared with a known ...
Page 49
Hop with Soft Sync The AD6636 can synchronize a change in NCO frequency and/or phase offset of multiple channels or chips under microprocessor control. The NCO hop hold-off counter, in conjunction with the soft hop enable bit and the channel ...
Page 50
AD6636 Figure 44 to Figure 47 illustrate a three byte block transfer through the serial port. Read and write operations with MSB_FIRST high and low are shown. Note that the figures show the sequence for write/read transfer, and actual data ...
Page 51
MSBFIRST SCS BLOCK END ADDRESS 0xaa SDI SDO MODE Figure 46. Serial Read of Three Bytes with MSB_FIRST = 1 (All Words are Written or Read MSB First) MSBFIRST SCS BLOCK START ADDRESS SDI SDO MODE Figure 47. Serial Read ...
Page 52
AD6636 SPI Mode Timing In SPI mode, the SCLK should run only when data is being transferred and SCS is logic low. If SCLK runs when SCS is logic high, the internal shift register continues to run and instruction words ...
Page 53
SPI Read During a typical read operation, a one-byte address and one- byte instruction are written to the serial port to instruct the internal control logic as to which registers are to be accessed. Register readback data shifts out on ...
Page 54
AD6636 SPORT Mode Timing In SPORT mode, the SCLK continuously runs, and the external SRFS and STFS signals are used to frame the data. Incoming framing signals SRFS (receive) and STFS (transmit) are sampled on the falling edges of SCLK. ...
Page 55
SPORT Read For a typical SPORT read operation, the user must write an address byte and instruction byte to the serial port to instruct the internal control logic as to which registers are to be MSBFIRST SCLK SCS SMODE SRFS ...
Page 56
AD6636 Programming Indirect Addressed Registers Using Serial Port This section gives examples for programming CRCF coefficient RAM (with an indirect addressing scheme) using the serial port (either SPI or SPORT modes). Though the following specific examples are for CRCF coefficient ...
Page 57
LSB_FIRST Mode Using Single-Byte Block Transfers SerialWrite(0x98); //CRCF Start Address SerialWrite(0x01); SerialWrite(0x00); SerialWrite(0x99); //CRCF Final Address SerialWrite(0x01); SerialWrite(N-1); //N is the number of coefficients for (i < N; i++) { // writing registers SerialWrite(0x9C); //LSB written first SerialWrite(0x01); ...
Page 58
AD6636 Connecting the AD6654 Serial Port to a Blackfin DSP In SPI mode, the Blackfin® DSP must act as a master to the AD6636 by providing the SCLK. SDO is an open-drain output, so that multiple slave devices can be ...
Page 59
Motorola (MNM) Mode The programming port performs synchronous Motorola-style reads and writes on the positive edge of CPUCLK when RESET is inactive (active low signal). The A[7:0] bus provides the address to access and the D[15:0] bus (D[7:0], if the ...
Page 60
AD6636 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has four address locations. The memory map is roughly divided into four regions: global register map (Address 0x00 to Address 0x0B), input port register map ...
Page 61
Table 30. Memory Map 8-Bit Hex Address Byte 3 0x03 Open <7:6>, Channel Enable <5:0> 0x07 Open <15:11>, LVDS Control<10:0> (Default 0x06FC) 0x0B Interrupt Mask <15:0> ADC Input Port Register Map—Addresses 0x0C to 0x67 0x0F ADC Input Control <31:0> 0x13 ...
Page 62
AD6636 8-Bit Hex Address Byte 3 0x97 Open<15:12>, CRCF Control Register<11:0> 0x9B Open<15:0> 0x9F Open<7:0> 0xA3 Open<15:11>, AGC Control Register<10:0> 0xA7 Open<15:12>, AGC Update Decimation<11:0> 0xAB Open<15:12>, AGC Error Threshold <11:0> 0xAF Open<7:0> 0xB3 Open<7:0> 0xB7 Open<7:0> 0xBB Open <15:0> ...
Page 63
Note that if the access bits are set for more than one channel during write access, all channels with access are written with the same data. This is especially useful when more than one channel has similar configurations. During a ...
Page 64
AD6636 When this bit is cleared, the output for the LVDS controller is taken from manual calibration value (Bits <7:0> of this register). <7:4>: These bits are open. <3:0>: Manual Calibration Value Bits. The value of these bits is used ...
Page 65
Channel 1 Data Ready Enable Bit. Similar to Bit <9> for Channel 1. <4>: Channel 0 Data Ready Enable Bit. Similar to Bit <9> for Channel 0. <3>: ADC Port D Power Monitoring Enable Bit. When this bit is ...
Page 66
AD6636 <10>: ADC Port C CLK Invert Bit. Similar to Bit <11> for ADC Port C. <9>: ADC Port B CLK Invert Bit. Similar to Bit <11> for ADC Port B. <8>: ADC Port A CLK Invert Bit. Similar to ...
Page 67
Port CD DC Correction Enable Bit. When the dc correction enable bit is set, the dc offset correction function of the I/Q correction block for the AB port is enabled. When cleared, the dc offset correction value is given ...
Page 68
AD6636 Port A Power Monitor Period <23:0> This register is used in the power monitoring logic to set the period of time for which ADC input data is monitored. This value represents the monitor period in number of ADC port ...
Page 69
NCO Bypass Bit. When this bit is set, the NCO is bypassed and shuts down for power savings. When a NCO frequency required, this bit can be used for power savings. When this ...
Page 70
AD6636 MRCF Control Register <12:0> <12:10>: MRCF Data Select Bits. These bits are used to select the input source for the MRCF filter. Each MRCF filter can be driven by output from the HB2 filter of any channel independ- ently. ...
Page 71
DRCF Taps <6:0> This register is written with one less than the number of taps that are calculated by the DRCF filter. The filter length is given by the decimal value of this register plus 1. A value of 0 ...
Page 72
AD6636 <7:5>: AGC Word Length Control Bits. These bits define the word length of the AGC output. The output word can be 4 bits to 8 bits, 10 bits, 12 bits bits wide. Table 42 shows the possible ...
Page 73
Number of AGC Average Samples. This defines the number of samples to be averaged before they are sent to the CIC decimating filter (see Table 43). Table 43. Number of AGC Average Samples AGC Average Samples <1:0> Number of ...
Page 74
AD6636 <15>: Port B Append RSSI Bit. When this bit is set, an RSSI word is appended to every I/Q output sample, irrespective of whether or not the RSSI word is updated in the AGC. When this bit is cleared, ...
Page 75
Stream Control Bits. These bits are described in Table 46. Table 46. Stream Control Bits Stream Output Streams (str0, str1, Control Bits str2, str3, str4, str5) 0000 Ch 0/Ch 1 combined ...
Page 76
AD6636 AGC3, RSSI Output <11:0> This read-only register provides the latest RSSI output sample from AGC3. This register is updated only when AGC3 is enabled and operating. AGC4, RSSI Output <11:0> This read-only register provides the latest RSSI output sample ...
Page 77
DESIGN NOTES The following guidelines describe circuit connections, layout requirements, and programming procedures for the AD6636. The designer should review these guidelines before starting the system design and layout. • The AD6636 requires the following power-up sequence. The VDDCORE (1.8 ...
Page 78
AD6636 If JTAG is used, the designer should ensure that the TRST pin is pulled low during power-up. After the power supplies have settled to nominal values (1.8 V and 3.3 V), the TRST pin can be pulled high for ...
Page 79
... OUTLINE DIMENSIONS 1.85* 1.71 1.40 ORDERING GUIDE Model Temperature Range 1 AD6636BBCZ −40°C to +85°C AD6636CBCZ 1 −40°C to +85°C AD6636BC/PCB Pb-free part. 17.20 17. 16.80 15 BALL A1 CORNER 15.00 BSC SQ TOP VIEW 1.00 BSC DETAIL A DETAIL A SEATING PLANE BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-192-AAF-1 EXCEPT FOR DIMENSIONS INDICATED BY A " ...
Page 80
AD6636 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04998–0–6/05(A) Rev Page ...