IC RCVR ASK/FSK UHF 433MHZ 20SSO

ATA8204P3-TKQY

Manufacturer Part NumberATA8204P3-TKQY
DescriptionIC RCVR ASK/FSK UHF 433MHZ 20SSO
ManufacturerAtmel
ATA8204P3-TKQY datasheet
 

Specifications of ATA8204P3-TKQY

Frequency433MHzSensitivity-115dBm
Data Rate - Maximum10 kbpsModulation Or ProtocolASK, FSK
ApplicationsGeneral PurposeCurrent - Receiving8.5mA
Data InterfacePCB, Surface MountAntenna ConnectorPCB, Surface Mount
FeaturesRSSI EquippedVoltage - Supply4.5 V ~ 5.5 V
Operating Temperature-40°C ~ 85°CPackage / Case20-SOIC (0.200", 5.30mm Width)
Pin Count20Screening LevelIndustrial
Lead Free Status / RoHS StatusLead free / RoHS CompliantMemory Size-
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Features
Frequency Receiving Range of (3 Versions)
– f
= 312.5 MHz to 317.5 MHz or
0
– f
= 431.5 MHz to 436.5 MHz or
0
– f
= 868 MHz to 870 MHz
0
30 dB Image Rejection
Receiving Bandwidth
– B
= 300 kHz for 315 MHz/433 MHz Version
IF
– B
= 600 kHz for 868 MHz Version
IF
Fully Integrated LC-VCO and PLL Loop Filter
Very High Sensitivity with Power Matched LNA
– ATA8203/ATA8204:
–107 dBm, FSK, BR_0 (1.0 kbit/s to 1.8 kBit/s), Manchester, BER 10E-3
–113 dBm, ASK, BR_0 (1.0 kbit/s to 1.8 kBit/s), Manchester, BER 10E-3
– ATA8205:
–105 dBm, FSK, BR_0 (1.0 kbit/s to 1.8 kBit/s), Manchester, BER 10E-3
–111 dBm, ASK, BR_0 (1.0 kbit/s to 1.8 kBit/s), Manchester, BER 10E-3
High System IIP3
– –18 dBm at 868 MHz
– –23 dBm at 433 MHz
– –24 dBm at 315 MHz
System 1-dB Compression Point
– –27.7 dBm at 868 MHz
– –32.7 dBm at 433 MHz
– –33.7 dBm at 315 MHz
High Large-signal Capability at GSM Band (Blocking –33 dBm at +10 MHz,
IIP3 = –24 dBm at +20 MHz)
Logarithmic RSSI Output
XTO Start-up with Negative Resistor of 1.5 k
5V to 20V Automotive Compatible Data Interface
Data Clock Available for Manchester and Bi-phase-coded Signals
Programmable Digital Noise Suppression
Low Power Consumption Due to Configurable Polling
Temperature Range –40°C to +85°C
ESD Protection 2 kV HBM, All Pins
Communication to Microcontroller Possible using a Single Bi-directional Data Line
Low-cost Solution Due to High Integration Level with Minimum External Circuitry
Requirements
Supply Voltage Range 4.5V to 5.5V
Benefits
Low BOM List Due to High Integration
Use of Low-cost 13 MHz Crystal
Lowest Average Current Consumption for Application Due to Self Polling Feature
Reuse of ATA5743 Software
World-wide Coverage with One PCB Due to 3 Versions are Pin Compatible
Industrial UHF
ASK/FSK
Receiver
ATA8203
ATA8204
ATA8205
9121B–INDCO–04/09

ATA8204P3-TKQY Summary of contents

  • Page 1

    Features • Frequency Receiving Range of (3 Versions) – 312.5 MHz to 317.5 MHz or 0 – 431.5 MHz to 436.5 MHz or 0 – 868 MHz to 870 MHz 0 • ...

  • Page 2

    Description The ATA8203/ATA8204/ATA8205 is a multi-chip PLL receiver device supplied in an SSO20 package. It has been specially developed for the demands of RF low-cost data transmission sys- tems with data rates from 1 kBit kBbit/s in ...

  • Page 3

    Figure 1-2. Block Diagram CDEM RSSI SENS AVCC AGND DGND DVCC LNAREF LNA_IN LNA LNAGND 9121B–INDCO–04/09 ATA8203/ATA8204/ATA8205 FSK/ASK Dem_out Demodulator and Data Filter RSSI Limiter out RSSI IF Sensitivity Amp. reduction and Control Logic 4. Order MHz ...

  • Page 4

    Pin Configuration Figure 2-1. Pinning SSO20 Table 2-1. Pin Description Pin Symbol 1 SENS 2 IC_ACTIVE 3 CDEM 4 AVCC 5 TEST 1 6 RSSI 7 AGND 8 LNAREF 9 LNA_IN 10 LNAGND 11 TEST 2 12 TEST 3 ...

  • Page 5

    RF Front-end The RF front-end of the receiver is a low-IF heterodyne configuration that converts the input sig- nal into about 1 MHz IF signal with a typical image rejection of 30 dB. According to Figure 1-2 on page ...

  • Page 6

    To determine 950 kHz. To achieve a good accuracy of the filter corner frequencies, the filter is tuned by IF the crystal frequency ...

  • Page 7

    Figure 4-1. The output voltage of the RSSI amplifier is internally compared to a threshold voltage V V Th_red SENS and GND or V means possible to operate the receiver at a lower sensitivity Sens nect ...

  • Page 8

    FSK/ASK Demodulator and Data Filter The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set using the bit ASK/_FSK in the OPMODE register. ...

  • Page 9

    Receiving Characteristics The RF receiver ATA8203/ATA8204/ATA8205 can be operated with and without a SAW front-end filter typical automotive application, a SAW filter is used to achieve better selectiv- ity and large signal capability. The receiving frequency response ...

  • Page 10

    Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor- responding transmitter. This is achieved using the polling circuit. This circuit enables the signal path periodically ...

  • Page 11

    The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range), which is defined in the OPMODE register. This clock cycle T formulas: BR_Range = 8. Polling Mode According to three different modes. In sleep mode the ...

  • Page 12

    Figure 8-1. Polling Mode Flow Chart Sleep Mode: All circuits for signal processing are disabled. Only XTO and Polling logic are enabled. Output level on Pin IC_ACTIVE = > low Soff T = Sleep Sleep Start-up ...

  • Page 13

    Bit-check Mode In bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 ...

  • Page 14

    For best noise immunity using a low span between T achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A “11111...” “10101...” sequence in Manchester or Bi-phase is suitable for this. A good ...

  • Page 15

    Figure 8-5. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min) (Lim_min = 14, Lim_max = 24) IC_ACTIVE Bit check Dem_out Bit-check 0 counter T Start-up Start-up mode Figure 8-6. Timing Diagram for Failed Bit Check (Condition: CV_Lim (Lim_min ...

  • Page 16

    Digital Signal Processing The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal data. This processing depends on the selected baud-rate range (BR_Range). extended clock cycle T ...

  • Page 17

    Figure 8-9. Steady L State Limited DATA Output Pattern After Transmission IC_ACTIVE Bit check Dem_out Data_out (DATA) Start-up mode After the end of a data transmission, the receiver remains active. Depending of the bit Noise_Disable in the OPMODE register, the ...

  • Page 18

    Figure 8-10. Timing Diagram of the OFF Command using Pin DATA IC_ACTIVE Out1 (microcontroller) Data_out (DATA) X Serial bi-directional X data line Receiving mode Figure 8-11. Timing Diagram of the OFF Command using Pin POLLING/_ON IC_ACTIVE POLLING/_ON Data_out (DATA) Serial ...

  • Page 19

    Figure 8-11 set the receiver back to polling mode using pin POLLING/_ON. The pin POLLING/_ON must be held to low for the time period the polling mode is active and the sleep time T on3 Using the ...

  • Page 20

    Use the function of the data clock only in conjunction with the bit check recom- mended. If the bit check is set the receiver is set to receiving mode using the pin ...

  • Page 21

    Figure 9-3. Data_out (DATA) DATA_CLK Figure 9-4. Data_out (DATA) DATA_CLK The delay of the data clock is calculated as follows the delay between the internal signals Data_Out and Data_In. For the rising edge, t Delay1 depends on ...

  • Page 22

    Figure 9-5. Figure 9-6. ATA8203/ATA8204/ATA8205 22 Timing Characteristic of the Data Clock (Rising Edge on Pin DATA) Data_Out 0. 0. Serial bi-directional S II data line Data_In DATA_CLK t Delay1 ...

  • Page 23

    Digital Noise Suppression After a data transmission, digital noise appears on the data output (see Digital Noise at the End of the Data Stream”). To prevent digital noise keeping the connected microcontroller busy, it can be suppressed in two ...

  • Page 24

    Figure 10-3. Occurrence of a Pulse at the End of the Data Stream Data_out (DATA) DATA_CLK 10.2 Controlled Noise Suppression by the Microcontroller Digital noise appears at the end of a valid data stream if the bit Noise_Disable (see on ...

  • Page 25

    Configuring the Receiver The ATA8203/ATA8204/ATA8205 receiver is configured using two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bidirectional DATA port. If the register content has changed due to a voltage ...

  • Page 26

    The following tables illustrate the effect of the individual configuration words. The default config- uration is highlighted for each word. BR_Range sets the appropriate baud-rate range and simultaneously defines XLim. XLim is used to define the bit-check limits T 11-11 ...

  • Page 27

    Table 11-7. Sleep4 ... 0 ... Table 11-8. Table 11-9. Noise Suppression 9121B–INDCO–04/09 ATA8203/ATA8204/ATA8205 Effect of the Configuration Word Sleep Sleep Sleep3 Sleep2 Sleep1 ...

  • Page 28

    Table 11-10. Effect of the Configuration Word Lim_min (1) Lim_min (Lim_min < not Applicable) Lim_min5 Lim_min4 Lim_min3 ...

  • Page 29

    Conservation of the Register Information The ATA8203/ATA8204/ATA8205 uses an integrated power-on reset and brown-out detection circuitry as a mechanism to preserve the RAM register information. According to below the threshold voltage V tion registers in that condition. The POR ...

  • Page 30

    Programming the Configuration Register Figure 13-1. Timing of the Register Programming IC_ACTIVE Out1 (microcontroller) Data_out (DATA) X Serial bi-directional X data line Receiving mode Figure 13-2. Data Interface V = 4.5V to 5.5V S 0V/5V Input Interface Data_in Data_out ...

  • Page 31

    Bit 15 is followed by the equivalent time window t9. During this window, the equivalence acknowledge pulse t8 (E_Ack) occurs if the just programmed mode word is equivalent to the mode word that was already stored in that register. E_Ack ...

  • Page 32

    Data Interface The data interface (see be connected using the pull-up resistor R The applicable pull-up resistor R selected BR_range (see Table 14- Figure 14-1. Application Circuit 4.7 µF 10% GND ...

  • Page 33

    Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated ...

  • Page 34

    Electrical Characteristics ATA8203 All parameters refer to GND 25°C, V amb Test No. Parameter Conditions Symbol 1 Basic Clock Cycle of the Digital Circuitry Basic clock 1.1 T cycle BR_Range0 Extended BR_Range1 1.2 basic clock T BR_Range2 ...

  • Page 35

    Electrical Characteristics ATA8203 (Continued) All parameters refer to GND 25°C, V amb Test No. Parameter Conditions Symbol Minimum time period between BR_Range = edges at pin DATA BR_Range0 (see Figure BR_Range1 3.3 4-2 and BR_Range2 t DATA_min ...

  • Page 36

    Electrical Characteristics ATA8203 (Continued) All parameters refer to GND 25°C, V amb Test No. Parameter Conditions Symbol 4 Configuration of the Receiver (see Frequency is Frequency of stable within 4.1 the reset after marker ...

  • Page 37

    Electrical Characteristics ATA8204, ATA8205 All parameters refer to GND 25°C, V amb Test No. Parameter Conditions Symbol 6 Basic Clock Cycle of the Digital Circuitry Basic clock 6.1 T cycle BR_Range0 Extended BR_Range1 6.2 basic clock T ...

  • Page 38

    Electrical Characteristics ATA8204, ATA8205 (Continued) All parameters refer to GND 25°C, V amb Test No. Parameter Conditions Symbol Minimum time period between BR_Range = edges at pin DATA BR_Range0 (see Figure BR_Range1 8.3 4-2 and BR_Range2 t ...

  • Page 39

    Electrical Characteristics ATA8204, ATA8205 (Continued) All parameters refer to GND 25°C, V amb Test No. Parameter Conditions Symbol 9 Configuration of the Receiver (see Frequency is Frequency of stable within 9.1 the reset after ...

  • Page 40

    Electrical Characteristics ATA8203, ATA8204, ATA8205 All parameters refer to GND 25°C, V amb No. Parameters 11 Current Consumption 11.1 Current consumption 12 LNA, Mixer, Polyphase Low-pass and IF Amplifier (Input Matched According to 12.1 Third-order intercept point ...

  • Page 41

    Electrical Characteristics ATA8203, ATA8204, ATA8205 (Continued) All parameters refer to GND 25°C, V amb No. Parameters Static capacitance at pin 13.6 XTAL1 to GND Static capacitance at pin 13.7 XTAL2 to GND Crystal series resistor Rm at ...

  • Page 42

    Electrical Characteristics ATA8203, ATA8204, ATA8205 (Continued) All parameters refer to GND 25°C, V amb No. Parameters Input sensitivity FSK 14.5 300 kHz IF filter (ATA8203/ATA8204) Input sensitivity FSK 14.6 600 kHz IF filter (ATA8205) Sensitivity variation FSK ...

  • Page 43

    Electrical Characteristics ATA8203, ATA8204, ATA8205 (Continued) All parameters refer to GND 25°C, V amb No. Parameters Sensitivity variation FSK for the full operating range 14.8 including IF filter compared 25°C, amb ...

  • Page 44

    Electrical Characteristics ATA8203, ATA8204, ATA8205 (Continued) All parameters refer to GND 25°C, V amb No. Parameters 14.18 Reduced sensitivity Reduced sensitivity variation 14.19 over full operating range Reduced sensitivity variation 14.20 for different values of R Sense ...

  • Page 45

    ... Ordering Information Extended Type Number ATA8203P3-TKQY ATA8204P3-TKQY ATA8205P6-TKQY 21. Package Information 0.25 ±0. Drawing-No.: 6.543-5056.01-4 Issue: 1; 10.03.04 22. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 9121B-INDCO-04/09 9121B–INDCO–04/09 ...

  • Page 46

    ... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...