ATA8204P3-TKQY Atmel, ATA8204P3-TKQY Datasheet
ATA8204P3-TKQY
Specifications of ATA8204P3-TKQY
Related parts for ATA8204P3-TKQY
ATA8204P3-TKQY Summary of contents
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Features • Frequency Receiving Range of (3 Versions) – 312.5 MHz to 317.5 MHz or 0 – 431.5 MHz to 436.5 MHz or 0 – 868 MHz to 870 MHz 0 • ...
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Description The ATA8203/ATA8204/ATA8205 is a multi-chip PLL receiver device supplied in an SSO20 package. It has been specially developed for the demands of RF low-cost data transmission sys- tems with data rates from 1 kBit kBbit/s in ...
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Figure 1-2. Block Diagram CDEM RSSI SENS AVCC AGND DGND DVCC LNAREF LNA_IN LNA LNAGND 9121B–INDCO–04/09 ATA8203/ATA8204/ATA8205 FSK/ASK Dem_out Demodulator and Data Filter RSSI Limiter out RSSI IF Sensitivity Amp. reduction and Control Logic 4. Order MHz ...
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Pin Configuration Figure 2-1. Pinning SSO20 Table 2-1. Pin Description Pin Symbol 1 SENS 2 IC_ACTIVE 3 CDEM 4 AVCC 5 TEST 1 6 RSSI 7 AGND 8 LNAREF 9 LNA_IN 10 LNAGND 11 TEST 2 12 TEST 3 ...
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RF Front-end The RF front-end of the receiver is a low-IF heterodyne configuration that converts the input sig- nal into about 1 MHz IF signal with a typical image rejection of 30 dB. According to Figure 1-2 on page ...
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To determine 950 kHz. To achieve a good accuracy of the filter corner frequencies, the filter is tuned by IF the crystal frequency ...
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Figure 4-1. The output voltage of the RSSI amplifier is internally compared to a threshold voltage V V Th_red SENS and GND or V means possible to operate the receiver at a lower sensitivity Sens nect ...
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FSK/ASK Demodulator and Data Filter The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set using the bit ASK/_FSK in the OPMODE register. ...
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Receiving Characteristics The RF receiver ATA8203/ATA8204/ATA8205 can be operated with and without a SAW front-end filter typical automotive application, a SAW filter is used to achieve better selectiv- ity and large signal capability. The receiving frequency response ...
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Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor- responding transmitter. This is achieved using the polling circuit. This circuit enables the signal path periodically ...
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The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range), which is defined in the OPMODE register. This clock cycle T formulas: BR_Range = 8. Polling Mode According to three different modes. In sleep mode the ...
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Figure 8-1. Polling Mode Flow Chart Sleep Mode: All circuits for signal processing are disabled. Only XTO and Polling logic are enabled. Output level on Pin IC_ACTIVE = > low Soff T = Sleep Sleep Start-up ...
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Bit-check Mode In bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 ...
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For best noise immunity using a low span between T achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A “11111...” “10101...” sequence in Manchester or Bi-phase is suitable for this. A good ...
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Figure 8-5. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min) (Lim_min = 14, Lim_max = 24) IC_ACTIVE Bit check Dem_out Bit-check 0 counter T Start-up Start-up mode Figure 8-6. Timing Diagram for Failed Bit Check (Condition: CV_Lim (Lim_min ...
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Digital Signal Processing The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal data. This processing depends on the selected baud-rate range (BR_Range). extended clock cycle T ...
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Figure 8-9. Steady L State Limited DATA Output Pattern After Transmission IC_ACTIVE Bit check Dem_out Data_out (DATA) Start-up mode After the end of a data transmission, the receiver remains active. Depending of the bit Noise_Disable in the OPMODE register, the ...
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Figure 8-10. Timing Diagram of the OFF Command using Pin DATA IC_ACTIVE Out1 (microcontroller) Data_out (DATA) X Serial bi-directional X data line Receiving mode Figure 8-11. Timing Diagram of the OFF Command using Pin POLLING/_ON IC_ACTIVE POLLING/_ON Data_out (DATA) Serial ...
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Figure 8-11 set the receiver back to polling mode using pin POLLING/_ON. The pin POLLING/_ON must be held to low for the time period the polling mode is active and the sleep time T on3 Using the ...
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Use the function of the data clock only in conjunction with the bit check recom- mended. If the bit check is set the receiver is set to receiving mode using the pin ...
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Figure 9-3. Data_out (DATA) DATA_CLK Figure 9-4. Data_out (DATA) DATA_CLK The delay of the data clock is calculated as follows the delay between the internal signals Data_Out and Data_In. For the rising edge, t Delay1 depends on ...
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Figure 9-5. Figure 9-6. ATA8203/ATA8204/ATA8205 22 Timing Characteristic of the Data Clock (Rising Edge on Pin DATA) Data_Out 0. 0. Serial bi-directional S II data line Data_In DATA_CLK t Delay1 ...
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Digital Noise Suppression After a data transmission, digital noise appears on the data output (see Digital Noise at the End of the Data Stream”). To prevent digital noise keeping the connected microcontroller busy, it can be suppressed in two ...
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Figure 10-3. Occurrence of a Pulse at the End of the Data Stream Data_out (DATA) DATA_CLK 10.2 Controlled Noise Suppression by the Microcontroller Digital noise appears at the end of a valid data stream if the bit Noise_Disable (see on ...
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Configuring the Receiver The ATA8203/ATA8204/ATA8205 receiver is configured using two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bidirectional DATA port. If the register content has changed due to a voltage ...
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The following tables illustrate the effect of the individual configuration words. The default config- uration is highlighted for each word. BR_Range sets the appropriate baud-rate range and simultaneously defines XLim. XLim is used to define the bit-check limits T 11-11 ...
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Table 11-7. Sleep4 ... 0 ... Table 11-8. Table 11-9. Noise Suppression 9121B–INDCO–04/09 ATA8203/ATA8204/ATA8205 Effect of the Configuration Word Sleep Sleep Sleep3 Sleep2 Sleep1 ...
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Table 11-10. Effect of the Configuration Word Lim_min (1) Lim_min (Lim_min < not Applicable) Lim_min5 Lim_min4 Lim_min3 ...
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Conservation of the Register Information The ATA8203/ATA8204/ATA8205 uses an integrated power-on reset and brown-out detection circuitry as a mechanism to preserve the RAM register information. According to below the threshold voltage V tion registers in that condition. The POR ...
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Programming the Configuration Register Figure 13-1. Timing of the Register Programming IC_ACTIVE Out1 (microcontroller) Data_out (DATA) X Serial bi-directional X data line Receiving mode Figure 13-2. Data Interface V = 4.5V to 5.5V S 0V/5V Input Interface Data_in Data_out ...
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Bit 15 is followed by the equivalent time window t9. During this window, the equivalence acknowledge pulse t8 (E_Ack) occurs if the just programmed mode word is equivalent to the mode word that was already stored in that register. E_Ack ...
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Data Interface The data interface (see be connected using the pull-up resistor R The applicable pull-up resistor R selected BR_range (see Table 14- Figure 14-1. Application Circuit 4.7 µF 10% GND ...
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Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated ...
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Electrical Characteristics ATA8203 All parameters refer to GND 25°C, V amb Test No. Parameter Conditions Symbol 1 Basic Clock Cycle of the Digital Circuitry Basic clock 1.1 T cycle BR_Range0 Extended BR_Range1 1.2 basic clock T BR_Range2 ...
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Electrical Characteristics ATA8203 (Continued) All parameters refer to GND 25°C, V amb Test No. Parameter Conditions Symbol Minimum time period between BR_Range = edges at pin DATA BR_Range0 (see Figure BR_Range1 3.3 4-2 and BR_Range2 t DATA_min ...
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Electrical Characteristics ATA8203 (Continued) All parameters refer to GND 25°C, V amb Test No. Parameter Conditions Symbol 4 Configuration of the Receiver (see Frequency is Frequency of stable within 4.1 the reset after marker ...
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Electrical Characteristics ATA8204, ATA8205 All parameters refer to GND 25°C, V amb Test No. Parameter Conditions Symbol 6 Basic Clock Cycle of the Digital Circuitry Basic clock 6.1 T cycle BR_Range0 Extended BR_Range1 6.2 basic clock T ...
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Electrical Characteristics ATA8204, ATA8205 (Continued) All parameters refer to GND 25°C, V amb Test No. Parameter Conditions Symbol Minimum time period between BR_Range = edges at pin DATA BR_Range0 (see Figure BR_Range1 8.3 4-2 and BR_Range2 t ...
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Electrical Characteristics ATA8204, ATA8205 (Continued) All parameters refer to GND 25°C, V amb Test No. Parameter Conditions Symbol 9 Configuration of the Receiver (see Frequency is Frequency of stable within 9.1 the reset after ...
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Electrical Characteristics ATA8203, ATA8204, ATA8205 All parameters refer to GND 25°C, V amb No. Parameters 11 Current Consumption 11.1 Current consumption 12 LNA, Mixer, Polyphase Low-pass and IF Amplifier (Input Matched According to 12.1 Third-order intercept point ...
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Electrical Characteristics ATA8203, ATA8204, ATA8205 (Continued) All parameters refer to GND 25°C, V amb No. Parameters Static capacitance at pin 13.6 XTAL1 to GND Static capacitance at pin 13.7 XTAL2 to GND Crystal series resistor Rm at ...
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Electrical Characteristics ATA8203, ATA8204, ATA8205 (Continued) All parameters refer to GND 25°C, V amb No. Parameters Input sensitivity FSK 14.5 300 kHz IF filter (ATA8203/ATA8204) Input sensitivity FSK 14.6 600 kHz IF filter (ATA8205) Sensitivity variation FSK ...
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Electrical Characteristics ATA8203, ATA8204, ATA8205 (Continued) All parameters refer to GND 25°C, V amb No. Parameters Sensitivity variation FSK for the full operating range 14.8 including IF filter compared 25°C, amb ...
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Electrical Characteristics ATA8203, ATA8204, ATA8205 (Continued) All parameters refer to GND 25°C, V amb No. Parameters 14.18 Reduced sensitivity Reduced sensitivity variation 14.19 over full operating range Reduced sensitivity variation 14.20 for different values of R Sense ...
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... Ordering Information Extended Type Number ATA8203P3-TKQY ATA8204P3-TKQY ATA8205P6-TKQY 21. Package Information 0.25 ±0. Drawing-No.: 6.543-5056.01-4 Issue: 1; 10.03.04 22. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 9121B-INDCO-04/09 9121B–INDCO–04/09 ...
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