ATA8204P3-TKQY Atmel, ATA8204P3-TKQY Datasheet - Page 17

• Manufacturer Part Number: ATA8204P3-TKQY
• Description: IC RCVR ASK/FSK UHF 433MHZ 20SSO
• Manufacturer: Atmel

Specifications of ATA8204P3-TKQY

• Frequency: 433MHz
• Sensitivity: -115dBm
• Data Rate - Maximum: 10 kbps
• Modulation Or Protocol: ASK, FSK
• Applications: General Purpose
• Current - Receiving: 8.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (0.200", 5.30mm Width)
• Pin Count: 20
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Figure 8-9.
8.7
9121B–INDCO–04/09
Data_out (DATA)
Switching the Receiver Back to Sleep Mode
IC_ACTIVE
Bit check
Dem_out
Steady L State Limited DATA Output Pattern After Transmission
Start-up mode
After the end of a data transmission, the receiver remains active. Depending of the bit
Noise_Disable in the OPMODE register, the output signal at pin DATA is high or random noise
pulses appear at pin DATA (see
edge-to-edge time period t
T
The receiver can be set back to polling mode via pin DATA or via pin POLLING/_ON.
When using pin DATA, this pin must be pulled to low by the connected microcontroller for the
period t1.
page
limited; however, exceeding the specified value to prevent erasing the reset marker is not rec-
ommended. Note also that an internal reset for the OPMODE and the LIMIT register is
generated if t1 exceeds the specified values. This item is explained in more detail in the
11. “Configuring the Receiver” on page
achieved by programming bit 1 to “1” during the register configuration. Only one sync pulse (t3)
is issued.
The duration of the OFF command is determined by the sum of t1, t2, and t10. The sleep time
T
Section 14. “Data Interface” on page
DATA_min
Sleep
30). The minimum value of t1 depends on the BR_Range. The maximum value for t1 is not
elapses after the OFF command. Note that the capacitive load at pin DATA is limited (see
.
Figure 8-10 on page 18
Bit-check mode
ee
of the majority of these noise pulses is equal or slightly higher than
illustrates the timing of the OFF command (see
Section 10. “Digital Noise Suppression” on page
32).
ATA8203/ATA8204/ATA8205
Receiving mode
25. Setting the receiver to sleep mode via DATA is
t
DATA_min
t
DATA_L_max
Figure 13-2 on
23). The
Section
17