IC RCVR UHF ASKFSK 868MHZ 20SOIC

ATA5760N-TGSY

Manufacturer Part NumberATA5760N-TGSY
DescriptionIC RCVR UHF ASKFSK 868MHZ 20SOIC
ManufacturerAtmel
ATA5760N-TGSY datasheet
 

Specifications of ATA5760N-TGSY

Frequency868MHzSensitivity-110dBm
Data Rate - Maximum10 kBaudModulation Or ProtocolASK, FSK
ApplicationsTelemetering and Security SystemsCurrent - Receiving7.8mA
Data InterfacePCB, Surface MountAntenna ConnectorPCB, Surface Mount
Voltage - Supply4.5 V ~ 5.5 VOperating Temperature-40°C ~ 105°C
Package / Case20-SOIC (0.300", 7.50mm Width)Lead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Memory Size-
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Features
Two Different IF Receiving Bandwidth Versions Are Available
(B
= 300 kHz or 600 kHz)
IF
Frequency Receiving Range of
f
= 868 MHz to 870 MHz or f
= 902 MHz to 928 MHz
0
0
30 dB Image Rejection
Receiving Bandwidth B
= 600 kHz for Low Cost 90-ppm Crystals and B
IF
55 ppm Crystals
Fully Integrated LC-VCO and PLL Loop Filter
Very High Sensitivity with Power Matched LNA
High System IIP3 (–16 dBm), System 1-dB Compression Point (–25 dBm)
High Large-signal Capability at GSM Band
(Blocking –30 dBm at +20 MHz, IIP3 = –12 dBm at +20 MHz)
5V to 20V Automotive Compatible Data Interface
Data Clock Available for Manchester- and Bi-phase-coded Signals
Programmable Digital Noise Suppression
Low Power Consumption Due to Configurable Polling
Temperature Range –40°C to +105°C
ESD Protection 2 kV HBM, All Pins
Communication to Microcontroller Possible Via a Single Bi-directional Data Line
Low-cost Solution Due to High Integration Level with Minimum External Circuitry
Requirements
1. Description
The ATA5760/ATA5761 is a multi-chip PLL receiver device supplied in an SO20 pack-
age. It has been especially developed for the demands of RF low-cost data
transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or
Bi-phase code. The receiver is well suited to operate with the Atmel’s PLL RF trans-
mitter T5750. Its main applications are in the areas of telemetering, security
technology and keyless-entry systems. It can be used in the frequency receiving
range of f
= 868 MHz to 870 MHz or f
0
transmission. All the statements made below refer to 868.3 MHz and 915.0 MHz
applications.
Figure 1-1.
System Block Diagram
UHF ASK/FSK
Remote control transmitter
T5750
PLL
XTO
Antenna
Antenna
VCO
Power
amp.
IF
= 902 MHz to 928 MHz for ASK or FSK data
0
UHF ASK/FSK
Remote control receiver
ATA5760/
ATA5761
Demod.
Control
IF Amp
PLL
XTO
LNA
VCO
= 300 kHz for
UHF ASK/FSK
Receiver
ATA5760
ATA5761
1...5
µC
4896D–RKE–08/08

ATA5760N-TGSY Summary of contents

  • Page 1

    ... It has been especially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with the Atmel’s PLL RF trans- mitter T5750. Its main applications are in the areas of telemetering, security technology and keyless-entry systems ...

  • Page 2

    Figure 1-2. Block Diagram CDEM SENS AVCC AGND DGND DVCC LNAREF LNA_IN LNA LNAGND ATA5760/ATA5761 2 FSK/ASK- Dem_out demodulator and data filter Rssi Limiter out RSSI IF Amp. Sensitivity- Polling circuit reduction control logic 4. Order f0 = 950 kHz/ ...

  • Page 3

    Pin Configuration Figure 2-1. Pinning SO20 Table 2-1. Pin Description Pin Symbol 1 SENS 2 IC_ACTIVE 3 CDEM 4 AVCC 5 TEST 1 6 AGND LNAREF 9 LNA_IN 10 LNAGND 11 TEST 2 12 TEST 3 ...

  • Page 4

    ... The resulting total LO tolerance of ±120 ppm agrees with the receiving bandwidth specification of the 600 kHz version of ATA5760/ATA5761 if the T5750 has also a total LO tolerance of ±120 ppm. For the ATA5760N3 crystals with ±55 ppm total tolerance are needed for receiver and transmit- ter to cope with the reduced IF-bandwidth. Figure 3-1. ...

  • Page 5

    The nominal frequency f using the following formula (low side injection determine f frequency tuned by the crystal frequency ...

  • Page 6

    ... MHz for the 915 MHz version. IF The nominal bandwidth is B ATA5760N3. 4.2 Limiting RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is R operated within its linear range, the best S/N ratio is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber ...

  • Page 7

    FSK/ASK Demodulator and Data Filter The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via the bit ASK/_FSK in the OPMODE register. ...

  • Page 8

    ... The receiving frequency response without a SAW front-end filter is illustrated in Figure 5-1 sion ATA5760N3. FSK mode exhibits a similar behavior. The plots are printed relatively to the maximum sensitivity SAW filter is used, an insertion loss of about 3 dB must be considered, but the overall selectivity is much better. ...

  • Page 9

    Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor- responding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically ...

  • Page 10

    Polling Mode According to three different modes. In sleep mode the signal processing circuitry is disabled for the time period T nal processing circuits are enabled and settled. In the following bit-check mode, the incoming data stream is analyzed ...

  • Page 11

    Figure 8-1. Polling Mode Flow Chart Sleep mode: All circuits for signal processing are disabled. Only XTO and Polling logic is enabled. Output level on Pin IC_ACTIVE => low Soff T = Sleep x X Sleep ...

  • Page 12

    Bit-check Mode In bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 ...

  • Page 13

    Using above formulas, Lim_min and Lim_max can be determined according to the required T Lim_min mum edge-to-edge time t “Receiving Mode” on page value of the upper limit is Lim_max = 63. If the calculated value for Lim_min is < ...

  • Page 14

    Figure 8-6. Timing Diagram for Failed Bit Check (Condition: CV_Lim (Lim_min = 14, Lim_max = 24) IC_ACTIVE Bit check Dem_out Bit-check- 0 counter T Start-up Start-up mode 8.4 Duration of the Bit Check If no transmitter signal is present during ...

  • Page 15

    Figure 8-7. Synchronization of the Demodulator Output T XClk Clock bit-check counter Dem_out Data_out (DATA) Figure 8-8. Debouncing of the Demodulator Output Dem_out Data_out (DATA) t DATA_min Figure 8-9. Steady L State Limited DATA Output Pattern After Transmission IC_ACTIVE Bit ...

  • Page 16

    Switching the Receiver Back to Sleep Mode The receiver can be set back to polling mode via pin DATA or via pin POLLING/_ON. When using pin DATA, this pin must be pulled to Low for the period t1 by ...

  • Page 17

    Figure 8-12. Activating the Receiving Mode via Pin POLLING/_ON IC_ACTIVE POLLING/_ON Data_out (DATA) Serial bi-directional data line Figure 8-11 on page 16 ING/_ON. The pin POLLING/_ON must be held to low for the time period t edge on pin POLLING/_ON ...

  • Page 18

    Data Clock The pin DATA_CLK makes a data shift clock available to sample the data stream into a shift reg- ister. Using this data clock, a microcontroller can easily synchronize the data stream. This clock can only be used ...

  • Page 19

    Figure 9-1. Dem_out Data_out (DATA) DATA_CLK Figure 9-2. Dem_out Data_out (DATA) DATA_CLK Figure 9-3. Dem_out Data_out (DATA) DATA_CLK 4896D–RKE–08/08 Timing Diagram of the Data Clock Preburst Bit check ok T '1' '1' '1' '1' Bit-check mode Data Clock Disappears Because ...

  • Page 20

    Figure 9-4. Dem_out Data_out (DATA) DATA_CLK The delay of the data clock is calculated as follows the delay between the internal signals Data_Out and Data_In. For the rising edge, t Delay1 depends on the capacitive load C ...

  • Page 21

    Figure 9-6. 10. Digital Noise Suppression After a data transmission, digital noise appears on the data output (see Preventing that digital noise keeps the connected microcontroller busy. It can be suppressed in two different ways. 10.1 Automatic Noise Suppression If ...

  • Page 22

    Figure 10-2. Automatic Noise Suppression Bit check ok Preburst Data_out (DATA) DATA_CLK Receiving mode, Bit-check data clock control mode logic active Figure 10-3. Occurrence of a Pulse at the End of the Data Stream Dem_out Data_out (DATA) DATA_CLK 10.2 Controlled ...

  • Page 23

    Configuration of the Receiver The T5760/T5761 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bidirectional DATA port. If the register contents have changed due to a ...

  • Page 24

    The following tables illustrate the effect of the individual configuration words. The default config- uration is highlighted for each word. BR_Range sets the appropriate baud-rate range and simultaneously defines XLim. XLim is used to define the bit-check limits T 11-11 ...

  • Page 25

    Table 11-7. Sleep4 ... 0 ... Table 11-8. Table 11-9. Noise Suppression 4896D–RKE–08/08 Effect of the Configuration Word Sleep Sleep Sleep3 Sleep2 Sleep1 ...

  • Page 26

    Table 11-10. Effect of the Configuration Word Lim_min (1) Lim_min (Lim_min < not Applicable) Lim_min5 Lim_min4 Lim_min3 ...

  • Page 27

    Conservation of the Register Information The ATA5760/ATA5761 implies an integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. According to below the threshold voltage V tion registers in that condition. Once ...

  • Page 28

    Programming the Configuration Register Figure 13-1. Timing of the Register Programming IC_ACTIVE Out1 (microcontroller) Data_out (DATA) X Serial bi-directional X data line Receiving mode Figure 13-2. Data Interface Data_In Data_out The ...

  • Page 29

    Bit 15 is followed by the equivalent time window t9. During this window, the equivalence acknowledge pulse t8 (E_Ack) occurs if the just programmed mode word is equivalent to the mode word that was already stored in that register. E_Ack ...

  • Page 30

    Figure 14-1. Application Circuit 4.7u 10% GND RF_IN C17 1.5p ±0.1p np0 Figure 14-2. Application Circuit 4.7µ 10% GND Toko LL1608-FS12NJ RF_IN 12 nH IN_GND C2 3 CASE_GND 3.3p 4 ...

  • Page 31

    Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated ...

  • Page 32

    Electrical Characteristics (Continued) All parameters refer to GND –40°C to +105°C, V amb (For typical values 5V 25°C) S amb Parameter Test Conditions Symbol Average bit-check time while polling applied Time ...

  • Page 33

    Electrical Characteristics (Continued) All parameters refer to GND –40°C to +105°C, V amb (For typical values 5V 25°C) S amb Parameter Test Conditions Symbol OFF command at pin POLLING/_O Ton2 N (see Figure ...

  • Page 34

    Electrical Characteristics (Continued) All parameters refer to GND –40°C to +105°C, V amb (For typical values 5V 25°C) S amb Parameter Test Conditions Symbol Data Clock (see Figure 10-2 on page 22 Minimum ...

  • Page 35

    Electrical Characteristics (continued) All parameters refer to GND –40°C to +105°C, V amb (For typical values 5V 25°C) S amb Parameters Local Oscillator Operating frequency range VCO Phase noise local oscillator Spurious of ...

  • Page 36

    Electrical Characteristics (continued) All parameters refer to GND –40°C to +105°C, V amb (For typical values 5V 25°C) S amb Parameters Sensitivity variation ASK for full operating range including IF filter compared to ...

  • Page 37

    Electrical Characteristics (continued) All parameters refer to GND –40°C to +105°C, V amb (For typical values 5V 25°C) S amb Parameters Lower cut-off frequency of the data filter Recommended CDEM for best performance ...

  • Page 38

    Electrical Characteristics (continued) All parameters refer to GND –40°C to +105°C, V amb (For typical values 5V 25°C) S amb Parameters Digital Ports Data output - Saturation voltage Low - max voltage at ...

  • Page 39

    ... Ordering Information Extended Type Number ATA5760N-TGSY ATA5760N-TGQY ATA5761N-TGSY ATA5761N-TGQY ATA5760N3-TGQY 20. Package Information Package SO20 Dimensions in mm 0.4 1. 4896D–RKE–08/08 Package Remarks SO20 Tube, for 868 MHz ISM band, Pb-free, B Taped and reeled, for 868 MHz ISM band, Pb-free, SO20 B SO20 ...

  • Page 40

    Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4896D-RKE-08/08 4896C-RKE-04/06 4896B-RKE-02/06 ATA5760/ATA5761 40 History Put datasheet in the newest template Page ...

  • Page 41

    ... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...