ATA5760N-TGSY Atmel, ATA5760N-TGSY Datasheet - Page 11

• Manufacturer Part Number: ATA5760N-TGSY
• Description: IC RCVR UHF ASKFSK 868MHZ 20SOIC
• Manufacturer: Atmel

Specifications of ATA5760N-TGSY

• Frequency: 868MHz
• Sensitivity: -110dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: Telemetering and Security Systems
• Current - Receiving: 7.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -

Figure 8-1.
Figure 8-2.
4896D–RKE–08/08
IC_ACTIVE
Bit check
Dem_out
Data_out (DATA)
(Number of checked Bits: 3)
Polling Mode Flow Chart
Timing Diagram for Complete Successful Bit Check
NO
Receiving mode:
The receiver is turned on permanently
and passes the data stream to the
connected microcontroller.
It can be set to Sleep mode through an
OFF command via Pin DATA or
POLLING/_ON.
Output level on Pin IC_ACTIVE => high
I
S
Sleep mode:
All circuits for signal processing are
disabled. Only XTO and Polling logic is
enabled.
Output level on Pin IC_ACTIVE => low
I
Start-up mode:
The signal processing circuits are
enabled. After the start-up time (T
all circuits are in stable
condition and ready to receive.
Output level on Pin IC_ACTIVE => high
Bit-check mode:
The incoming data stream is
analyzed. If the timing indicates a valid
transmitter signal, the receiver is set to
receiving mode. Otherwise it is set to
Sleep mode.
Output level on Pin IC_ACTIVE => high
I
T
I
T
T
S
S
S
= I
Sleep
Bit-check
Startup
= I
= I
= I
Start-up mode
Son
Soff
Son
Son
= Sleep x X
T
Start-up
OFF command
Bit check
Sleep
OK ?
x 1024 x T
YES
1/2 Bit
Clk
Startup
)
1/2 Bit
Bit-check mode
T
Bit-check
1/2 Bit
T
Sleep:
X
T
T
Startup
Sleep
Bit-check
Clk
Bit check ok
:
1/2 Bit
:
:
:
5-bit word defined by Sleep0 to
Sleep4 in OPMODE register
Extension factor defined by
XSleepStd
Basic clock cycle defined by f
and Pin MODE
Is defined by the selected baud rate
range and TClk. The baud-rate range
is defined by Baud0 and Baud1 in
the OPMODE register.
Depends on the result of the bit check
If the bit check is ok, T
depends on the number of bits to be
checked (N
utilized data rate.
If the bit check fails, the average
time period for that check depends
on the selected baud-rate range and
on T
defined by Baud0 and Baud1 in the
OPMODE register.
according to Table 9
1/2 Bit
Clk
. The baud-rate range is
1/2 Bit
Bit-check
ATA5760/ATA5761
) and on the
Receiving mode
Bit-check
XTO
11