ATA5760N-TGSY Atmel, ATA5760N-TGSY Datasheet - Page 13

• Manufacturer Part Number: ATA5760N-TGSY
• Description: IC RCVR UHF ASKFSK 868MHZ 20SOIC
• Manufacturer: Atmel

Specifications of ATA5760N-TGSY

• Frequency: 868MHz
• Sensitivity: -110dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: Telemetering and Security Systems
• Current - Receiving: 7.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -

Figure 8-4.
Figure 8-5.
4896D–RKE–08/08
Bit check
Bit check
IC_ACTIVE
Dem_out
Bit-check-
counter
IC_ACTIVE
Dem_out
Bit-check-
counter
(Lim_min = 14, Lim_max = 24)
(Lim_min = 14, Lim_max = 24)
Timing Diagram During Bit Check
Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
Start-up mode
Start-up mode
T
T
Using above formulas, Lim_min and Lim_max can be determined according to the required
T
mum edge-to-edge time t
“Receiving Mode” on page
value of the upper limit is Lim_max = 63.
If the calculated value for Lim_min is < 19, it is recommended to check 6 or 9 bits (N
prevent switching to receiving mode due to noise.
Figure 8-7 on page
bit-check limits Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing
circuits are enabled during T
fined during that period. When the bit check becomes active, the bit-check counter is clocked
with the cycle T
Figure 8-7 on page 15
is within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
ure 8-8 on page 15
bit check also fails if CV_Lim reaches Lim_max. This is illustrated in
0
Start-up
Start-up
0
Lim_min
, T
1
1
Lim_max
2 3 4 5 6
2 3 4 5 6
XClk
and T
T
.
7 8 1
1
XClk
the bit check fails as the value CV_Lim is lower than the limit Lim_min. The
15,
Bit-check mode
2
shows how the bit check proceeds if the bit-check counter value CV_Lim
3
XClk
T
Bit-check
Figure 8-8
2
4 5
. The time resolution defining T
3
1/2 Bit
ee
14. The lower limit should be set to Lim_min
4 5
6 7 8 9
Startup
(t
6 7 8 9
DATA_L_min
Bit check failed ( CV_Lim < Lim_min )
. The output of the ASK/FSK demodulator (Dem_out) is unde-
1/2 Bit
10
and
11 12
10
Bit-check mode
11 12 13 14
Figure 8-9 on page 15
T
, t
Bit-check
DATA_H_min
15 16 17 18 1 2 3 4 5 6
Bit check ok
Sleep mode
0
T
Sleep
) is defined according to the section
Lim_min
ATA5760/ATA5761
and T
illustrate the bit check for the
7 8 9 10 11 12 13 14 15 1 2 3 4
1/2 Bit
Figure 8-9 on page
Lim_max
Bit check ok
10. The maximum
is T
XClk
1/2 Bit
. The mini-
Bit-check
15.
Fig-
) to
13