TEA5766UK/N1-G ST-Ericsson Inc, TEA5766UK/N1-G Datasheet

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TEA5766UK/N1-G

Manufacturer Part Number
TEA5766UK/N1-G
Description
IC FM STEREO RADIO W/RDS 25WLCSP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of TEA5766UK/N1-G

Frequency
76MHz ~ 108MHz
Sensitivity
-111dBm
Modulation Or Protocol
FM
Applications
FM Radio Receiver
Current - Receiving
17mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Voltage - Supply
2.6 V ~ 3.6 V
Operating Temperature
-20°C ~ 85°C
Package / Case
25-WLCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Memory Size
-
Data Rate - Maximum
-
Other names
935281564023
Dear customer,
As from August 2
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
Company name - NXP B.V. is replaced with ST-NXP Wireless.
Copyright - the copyright notice at the bottom of each page “© NXP B.V. 200x. All
rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”.
Web site -
Contact information - the list of sales offices previously obtained by sending
an email to
under Contacts.
http://www.nxp.com
salesaddresses@nxp.com
nd
2008, the wireless operations of NXP have moved to a new company,
IMPORTANT NOTICE
is replaced with
, is now found at
http://www.stnwireless.com
http://www.stnwireless.com
www.stnwireless.com

Related parts for TEA5766UK/N1-G

TEA5766UK/N1-G Summary of contents

Page 1

IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...

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TEA5766UK Stereo FM radio + RDS Rev. 01 — 22 March 2007 1. General description The TEA5766UK is a single chip electronically tuned FM stereo radio with Radio Data System (RDS) and Radio Broadcast Data System (RBDS) demodulator and RDS/RBDS ...

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NXP Semiconductors I Interrupt flag I Interrupt line 3. Quick reference data Table 1. Quick reference data Under all conditions a reference clock of 32.768 kHz is present. Symbol Parameter General electrical parameters V analog supply voltage CCA V VCO ...

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C1 REFERENCE FREQIN BUFFER A6 AUTO POWER V CCA ALIGN SUPPLY IF LIMITER FILTER I/Q MIXER ÷2 1st RFIN1 RF AGC C6 RFIN2 LNA C5 GND(RF) prog. div out ref. div out TUNING SYSTEM VCO A2 A1 ...

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NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Ball configuration 6.2 Pin description Table 3. Symbol CPOUT LOOPSW LO1 LO2 V CC(VCO) V CCA SWPORT INTX GNDA RFIN1 FREQIN BUSEN GND(RF) RFIN2 V CCD GNDD GNDD ISS TMUTE DATA ...

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NXP Semiconductors Table 3. Symbol MPXOUT VAFL VAFR [1] The ISS pin the bus type can be selected, see 7. Functional description 7.1 Low noise RF amplifier The Low Noise Amplifier (LNA) input impedance together with the LC RF input ...

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NXP Semiconductors Formula for high-side injection DEC Formula for low-side injection DEC where: N DEC f = wanted tuning frequency (Hz intermediate frequency of 225 kHz reference frequency of 32.768 ...

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NXP Semiconductors 7.8 IF filter Fully integrated IF filter with a center frequency of 225 kHz. 7.9 FM demodulator Fully integrated FM quadrature demodulator. 7.10 IF counter 7.10.1 IF counter correct channel checking The received RF signal is converted down ...

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NXP Semiconductors 7.12.2 Hard mute With the MU bit of the TNCTRL register byte 2 (see VAFR can be hard-muted; this means they are put in high-impedance state. The same can be done by setting the bits Left Hard Mute ...

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NXP Semiconductors test mode the software port outputs signals according to selected by setting bit TM of register TESTREG (see disabled by the PUPD bits (see 7.16 Standby mode With the PUPD[1:0] (power-up/power-down) bits the radio can be put in ...

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NXP Semiconductors 7.19 RDS/RBDS decoder The RDS decoder provides block synchronization, error correction and flywheel function for reliable extraction of RDS or RBDS block data. Different modes of operation can be selected to fit different application requirements. Availability of new ...

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NXP Semiconductors Table 5. Bit IFFLAG [1] This table is valid until 31.25 ms after the tuning cycle has completed. It shows the outcome of the flag register when a read is done after INTX has gone ...

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NXP Semiconductors Fig 4. Flowchart auto search or preset 7.21 RDS update or alternative frequency jump A channel which transmits RDS data can have alternative channels which carry the same information. These alternative channel frequencies are in the RDS data, ...

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NXP Semiconductors The tuner can do an RDS update. This is a preset, but with count time. The tuner will jump to the alternative frequency and check the level and the IF count using a 2 ...

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NXP Semiconductors Fig 5. Flowchart RDS update 8. Interrupt handling 8.1 Interrupt register The first two bytes of the I flags. A flag is set when it is logic 1. Table 7. 7 DAVFLG Table 8. 7 DAVMSK TEA5766UK_1 Product ...

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NXP Semiconductors The interrupt flag register contains the flags set according to the behavior outlined in Section (hardware interrupt line) depending on the status of the corresponding mask bit in A logic 1 in the mask register enables the hardware ...

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INTFLAG data device S R ack 0R data ack address interrupt event ( interrupt flag bit interrupt mask bit INTX (1) Interrupt events that occur outside of the region A-B set their respective flag bits in ...

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INTFLAG MOSI R/ subaddress data W CS interrupt event (1) A interrupt flag bit interrupt mask bit INTX (1) Interrupt events that occur outside of the region A-B set their respective flag bits in the normal way immediately and can ...

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NXP Semiconductors 8.2 Interrupt flags and behavior 8.2.1 Multiple interrupt events If the interrupt mask register bit is set then the setting of an interrupt flag for that bit causes a hardware interrupt (INTX goes LOW). If the event occurs ...

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NXP Semiconductors If the LSYNCMSK bit is logic 0 and synchronization is lost the TEA5766UK automatically starts a new synchronization search. It will not generate a hardware interrupt. The host processor can wait until the RDS decoder is synchronized again; ...

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NXP Semiconductors After a search, a preset update the threshold for comparison is switched to the hysteresis level. The hysteresis level is set by the combination of SSL bits and the LHSW bit, which results in a ...

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NXP Semiconductors V CC interrupt event flag A flag B INTX read INTMSK write INTMSK (1) Flag is set immediately after the reset, because event is still present. (2) When flag is set next interrupts are blocked until read or ...

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NXP Semiconductors If a data block is decoded and a new data block arrives, INTX will go LOW again, the DAVFLG will be set, the last block will be shifted to the previous block and the last decoded block will ...

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NXP Semiconductors DAVFLG set on falling edge of DAVN signal, cleared on read BL register read INTFLG Bus registers decoder registers DOVF (data overflow) bit (1) Bit DOVF set when 2 new blocks received in BL ...

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NXP Semiconductors 9.2 DAV-B processing mode and fast PI search mode This mode is used when, for example, the receiver has been re-tuned to a new station and a fast search of the PI code (always contained in the A/C’-block) ...

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NXP Semiconductors 9.3 DAV-C reduced processing mode The DAV-C processing mode is very similar to DAV-A mode with the main exception that a data flag is only set after two new blocks are received. Hence the update rate is reduced ...

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NXP Semiconductors (1) Two new blocks have arrived in the BL and BP register. (2) Instant copy C (3) Instant copy of A (4) DAVFLG not cleared as no read is performed. (5) DAVFLG is reset when first new block ...

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NXP Semiconductors 9.4 Synchronization 9.4.1 Conditions for synchronization When the RDS decoder is turned on it must be synchronized to extract valid data from the MPX signal the decoder automatically initiates a search for synchronization. The conditions ...

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NXP Semiconductors 9.4.2 Modified Mobile Broadcast Service (MMBS) mode There are three synchronization modes, RDS, RBDS and MMBS. • RDS mode: the decoder can read and D blocks and synchronize and D blocks. ...

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RDS data A B DAVN DAVFLG reset of DAVFLG 0R 19R 0W 0R Read byte: 15R 15R (2) (3) 17R Blocking DAVFLG: at end of reading byte 15R or byte 17R (DAV-A, B/C) DAVFLG is forced to zero. Only after ...

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NXP Semiconductors 9.6 Error detection and reporting The TEA5766UK must report information on the number of errors corrected in the last and previously decoded blocks. This is reported in the ELB[1:0] and EPB[1:0] fields as shown in Table During synchronization ...

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NXP Semiconductors 2 10.2 I C-bus The full I January 2000 Write mode S b. Read mode ( START condition. ( acknowledge (SDA LOW). (3) NAK = non acknowledge (SDA HIGH). ( ...

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NXP Semiconductors Figure 15 FM and FM + RDS access. For simplicity the address, start, stop and acknowledge bits are not shown. The FM and RDS part have different I When the TEA5766UK is addressed with the FM radio address, ...

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NXP Semiconductors Table 10. Characteristics of the data output stage for fast mode and standard mode Symbol Parameter V LOW-level output OL1 voltage V LOW-level output OL3 voltage t output fall time of [1] The maximum fall time for the ...

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NXP Semiconductors 10.3 SPI-bus SPI stands for serial peripheral interface. TEA5766UK uses the SPI-bus in 3-wire mode, the data-in and data-out are combined to one bidirectional data line. For this application the SPI-bus works as a slave receiver or a ...

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NXP Semiconductors BUSEN CLOCK DATA - - A4 Fig 18. SPI transfer, 3 wire-mode BUSEN (CS) t SPIF t SPILEAD CLOCK (SPICLK) t SPIA DATA SLAVE MSB/LSB OUT (MISO OUTPUT) t SPIDSU DATA (MOSI MSB/LSB IN INPUT SPI ...

Page 37

NXP Semiconductors 11. Registers 11.1 Register map The reference for the register map is the Motorola SPI addressing. The actual register is in fact one long register, so the I Table 12. Register name SPI address INTREG FRQSET TNCTRL FRQCHK ...

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NXP Semiconductors Table 14. INTREG - SPI address Bit Symbol 2 SPI LEVFLAG FRRFLAG 08 0 BLFLAG 07 7 DAVMSK LSYNCMSK 04 4 ...

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NXP Semiconductors Table 16. TNCTRL - SPI address Bit Symbol 2 SPI IFCTC 10 2 AFM 09 1 SMUTE 08 0 SNC and 05 6 and 5 SSL[1:0] 04 ...

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NXP Semiconductors Table 18. TUNCHK - SPI address Bit Symbol 2 SPI STEREO 01 and 00 1 and 0 - [1] This does not switch the radio to mono or ...

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NXP Semiconductors Table 20. RSSI ADC search stop level 3 (SNR = 40 dBA) 5 (SNR = 46 dBA) 7 (SNR = 52 dBA) 10 (maximum SNR and maximum channel separation) Table 21. Test conditions: T de-emphasis = 50 s, ...

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NXP Semiconductors Table 22. RDSR1 - SPI address Bit Symbol 2 SPI BPID[2:0] 04 and 03 4 and 3 EPB[1: SYNC 01 1 RSTD 00 0 DOVF ...

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NXP Semiconductors Table 26. RDSW1 - SPI address Bit Symbol 2 SPI NWSY 14 and 13 6 and 5 SYM[1: RBDS 11 and 10 3 and 2 DAC[1: ...

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NXP Semiconductors 12. Limiting values Table 30. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V LO1 V LO2 V CCD V CCA stg T amb V esd [1] Machine model (L ...

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NXP Semiconductors Table 31. General characteristics Under all conditions a reference clock of 32.768 kHz is present. Symbol Parameter I current on pin VREFDIG VREFDIG f FM input frequency i(FM) T ambient temperature amb [1] Includes both analog supply current ...

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NXP Semiconductors Table 33. Characteristics …continued All AC values are given in RMS unless otherwise specified. The min and max values include spread due +85 C, reference ...

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NXP Semiconductors Table 33. Characteristics …continued All AC values are given in RMS unless otherwise specified. The min and max values include spread due +85 C, reference ...

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NXP Semiconductors Table 33. Characteristics …continued All AC values are given in RMS unless otherwise specified. The min and max values include spread due +85 C, reference ...

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NXP Semiconductors Table 33. Characteristics …continued All AC values are given in RMS unless otherwise specified. The min and max values include spread due +85 C, reference ...

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NXP Semiconductors Table 33. Characteristics …continued All AC values are given in RMS unless otherwise specified. The min and max values include spread due +85 C, reference ...

Page 51

C1 REFERENCE FREQIN BUFFER A6 AUTO V CCA ALIGN FILTER FM ANTENNA I/Q MIXER ÷2 1st FM N1 100 pF B6 RFIN1 AGC RFIN2 C6 120 nH LNA 47 pF GND(RF) C5 TUNING SYSTEM VCO A2 ...

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NXP Semiconductors Table 34. Symbol Parameter TEA5766UK_1 Product data sheet List of components 120 and 100 k 27 pF, 47 pF, 100 pF and 100 nF tolerance 10 % ...

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NXP Semiconductors 15. Package outline WLCSP25: wafer level chip-size package; 25 bumps; 3.3 x 3.25 x 0.6 mm bump A1 index area DIMENSIONS (mm are the original dimensions) A UNIT ...

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NXP Semiconductors 16. Soldering 16.1 Introduction to soldering WLCSP packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in Application Note AN10439 “Wafer ...

Page 55

NXP Semiconductors Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Fig 23. Temperature profiles for large and small components For further ...

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NXP Semiconductors 16.3.3 Rework In general, rework is not recommended. By rework we mean the process of removing the chip from the substrate and replacing it with a new chip chip is removed from the substrate, most solder ...

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NXP Semiconductors 18. Revision history Table 37. Revision history Document ID Release date TEA5766UK_1 20070322 TEA5766UK_1 Product data sheet Data sheet status Change notice Product data sheet - Rev. 01 — 22 March 2007 TEA5766UK Stereo FM radio + RDS ...

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NXP Semiconductors 19. Legal information 19.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

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NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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NXP Semiconductors 16.3.2 Quality of solder joint . . . . . . . . . . . . . . . . . . . 54 16.3.3 Rework . . . . . . . . . . . ...

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