SI4322-A0-FT Silicon Laboratories Inc, SI4322-A0-FT Datasheet
SI4322-A0-FT
Specifications of SI4322-A0-FT
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SI4322-A0-FT Summary of contents
Page 1
... FCC or ETSI conformance for unlicensed use in the 868 and 915 MHz bands. Used in conjunction with Silicon Labs’ FSK transmitters, the Si4322 is a flexible, low cost, and highly integrated solution that does not require production alignments. All required RF functions are integrated ...
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... An analog RSSI signal is also available. The RSSI settling time depends on the filter capacitor used. RSSI voltage P3 [V] P4 Input Power [dBm] Voltage on ARRSI pin vs. Input RF power P1 -65 dBm P2 -65 dBm P3 -100 dBm P4 -100 dBm Si4322 P1 P2 1300 mV 1000 mV 600 mV 300 mV 2 ...
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... Active mode can be initiated by setting the bits (in the Configuration Setting or Receiver Setting Command). Si4322 generates an interrupt signal on several events (wake- up timer timeout, low supply voltage detection, on-chip FIFO filled up). This signal can be used to wake up the microcontroller, effectively reducing the period the microcontroller has to be active ...
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... Crystal connection (other terminal of crystal to VSS) DI External reference input DO Reset output (active low) S Negative supply voltage AI RF differential signal input AI RF differential signal input S Positive supply voltage AO Analog RSSI output DO Valid Data Indicator output Si4322 VDI ARSSI VDD IN1 IN2 VSS nRES XTL / REF Description 4 ...
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... ON programmable in 0.1 V steps 2.0 larger glithches on the V dd generate a POR even above the threshold V POR for proper POR generation 0.1 0 Si4322 Max Units 6 +0 1000 V o 125 C o 260 2 Typ Max Units 10.5 12 µA 5 µ ...
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... MHz LNA: high gain LNA gain (0, -12dB) LNA gain (-6, -18dB) until the RSSI output goes high after the input signal exceeds the pre-programmed limit 5nF ARRSI Si4322 Typ Max Units 878.06 MHz 958.06 120 134 150 180 ...
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... Programmable in 0.5 pF steps, tolerance +/- 10% After V has reached 90% of final dd value Crystal ESR < 100 Ω Calibrated every 30 seconds (Note 4) 0.995 15 pF pure capacitive load 10 pF pure capacitive load Tolerance +/- 1 kHz Si4322 Min Typ Max Units MHz 20 kHz μs 30 μ ...
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... Data setup time (SDI transition to SCK rising edge Data hold time (SCK rising edge to SDI transition Data delay time OD Timing Diagram t SS nSEL SCK BIT15 BIT14 SDI SDO BIT15 BIT14 t OD BIT13 BIT8 BIT7 BIT13 BIT8 BIT7 Si4322 Minimum value [ns SHI t SH BIT1 BIT0 BIT1 BIT0 8 ...
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... Bits eb and et control the operation of the low battery detector and wake-up timer, respectively. They are enabled when the corresponding bit is set set the crystal is active during non-active mode. When dc bit is set it disables the clock output Si4322 POR 938Ah ...
Page 10
... The constant C is determined by the selected band as: Band [MHz] 868 915 VDI output 0 Digital RSSI Out (DRSSI) 1 Data Quality Detector Output (DQD) 0 Clock recovery lock 1 Always g0 G (dB relative to max. G) LNA - RSSIsetth [dBm -103 - - - - - - -61 RSSI = RSSI POR AD57h POR C080h + G setth LNA Si4322 10 ...
Page 11
... Strobe edge. When st goes to high, the actual latest calculated frequency error is stored into the output registers of the AFC block wake- m13 m12 m11 m10 elfc Clock Output Frequency [MHz rl1 rl0 POR E196h ms R POR m9 m8 C300h POR C213h of the detector 1.25 1.66 2 2.5 3. POR C687h Si4322 11 ...
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... OFFSET REGISTER IF IN<MinDEV THEN OUT=MinDEV used in auto ELSE operation OUT=IN mode CLK CLR RANGE LIMIT strobe STROBE output enable OUTPUT ENABLE Si4322 fres: 868MHz band: 20 kHz 915MHz band: 20 kHz ATGL** ASAME*** OFFS 12 BIT <3:0> 4 BIT ADDER FREQ. Fcorr<11:0> to synthesizer NOTE: * VDI (valid data indicator internal signal of the controller ...
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... Filter Type 0 Digital 1 Analog RC filter Δ BR/BR < 1/(29*N ) Clock recovery in fast mode: bit BR is bit rate difference between the transmitter and the receiver. N Δ POR sf ewi C462h POR C813h Δ BR/BR < 3/(29*N is the maximal number of bit Si4322 ) bit 13 ...
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... VDI 0 SYNC. WORD SYNC. WORD 2 Sync. Word X Detector logic HIGH 3 EN nRES s0* s1* Pad DATA I/O Port fifo enable* DIRECTION NOTE: * For details see the Output and FIFO Mode Command Si4322 POR CE87h FIFO WRITE Logic (simplified) FIFO_WRITE_DATA FIFO_WRITE_CLK FIFO_WRITE_EN nFIFO_RESET 14 ...
Page 15
... Bit 1-0 <f5:f4>: Upper two bits for selecting the 48 bit FIFO IT level together with the f3-f0 bits in the Output and FIFO Mode Command exlp ctls 0 dcal bw1 bw0 PLL bandwidth kHz kHz kHz 1 1 120 kHz Si4322 POR bw1 bw0 f5 f4 B0CAh 15 ...
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... The read command starts with a zero, whereas all other control commands start with a one. Therefore, after receiving the first bit of the control command the Si4322 identifies read command the first bit of the command is received, the receiver starts to clock out the status bits on the SDO output as follows: ...
Page 17
... SCK Power Saving Modes The different operating modes of the chip depend on the following control bits: Operating Mode Active Idle Sleep Standby 4 FO+4 /4, where f is the crystal oscillator frequency. ref ref (Configuration (Receiver Setting Setting Comand) Command Si4322 ex (Configuration Setting Command ...
Page 18
... Bit dcal in the Extended Features Command (page 15) controls the automatic calibration feature reset power-on and the automatic calibration is enabled. This is necessary to compensate for process tolerances. After one calibration cycle further (re)calibration can be disabled by setting this bit slow < 0 slow x Si4322 clock periods are not to scale T fast + T from the slow fast ) half cycle. The ...
Page 19
... AFC Control Command (bit 0). CRYSTAL SELECTION GUIDELINES The crystal oscillator of the Si4322 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8 0.5 pF steps. ...
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... PACKAGE INFORMATION 16-pin TSSOP Si4322 20 ...
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... This page has been intentionally left blank. Si4322 21 ...
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... ORDERING INFORMATION Si4322 Universal ISM Band FSK Receiver DESCRIPTION Si4322 16-pin TSSOP die Demo Boards and Development Kits DESCRIPTION ISM Chipset Development Kit Related Resources DESCRIPTION Antenna Selection Guide Antenna Development Guide Si4222 Universal ISM Band FSK Transmitter Note: Volume orders must include chip revision to be accepted. ...