SI4330-B1-FMR Silicon Laboratories Inc, SI4330-B1-FMR Datasheet

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SI4330-B1-FMR

Manufacturer Part Number
SI4330-B1-FMR
Description
IC RX ISM 240-960MHZ 20VQFN
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of SI4330-B1-FMR

Frequency
240MHz ~ 960MHz
Sensitivity
-121dBm
Data Rate - Maximum
256 kbps
Modulation Or Protocol
FSK, GFSK, OOK
Applications
Remote Control, RKE, Security Systems
Current - Receiving
18.5mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Features
RSSI Equipped
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-

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Si4330 ISM R
Features
Applications
Description
Silicon Laboratories’ Si4330 is a highly integrated, single chip wireless ISM
receiver. The high-performance EZRadioPRO
transmitters, receivers, and transceivers allowing the RF system designer to
choose the optimal wireless part for their application.
The Si4330 offers advanced radio features including continuous frequency
coverage from 240–960 MHz. The Si4330’s high level of integration offers
reduced BOM cost while simplifying the overall system design. The extremely low
receive sensitivity (–121 dBm) ensures extended range and improved link
performance. Built-in antenna diversity and support for frequency hopping can be
used to further extend range and enhance performance.
Additional system features such as an automatic wake-up timer, low battery
detector, 64 byte RX FIFO, automatic packet handling, and preamble detection
reduce overall current consumption and allow the use of a lower-cost system
MCU. An integrated temperature sensor, general purpose ADC, power-on-reset
(POR), and GPIOs further reduce overall system cost and size.
The Si4330’s digital receive architecture features a high-performance ADC and
DSP based modem which performs demodulation, filtering, and packet handling
for increased flexibility and performance.
An easy-to-use calculator is provided to quickly configure the radio settings,
simplifying customer's system design and reducing time to market.
Rev 1.0 12/09
Frequency Range = 240–960 MHz
Sensitivity = –121 dBm
Low Power Consumption

Data Rate = 0.123 to 256 kbps
FSK, GFSK, and OOK modulation
Power Supply = 1.8 to 3.6 V
Ultra low power shutdown mode
Digital RSSI
Wake-up timer
Auto-frequency calibration (AFC)
Clear channel assessment
Programmable RX BW 2.6–620 kHz
Programmable packet handler
Remote control
Home security & alarm
Telemetry
Personal data logging
Toy control
Tire pressure monitoring
Wireless PC peripherals
18.5 mA receive
ECEIVER
Copyright © 2009 by Silicon Laboratories
Programmable GPIOs
Embedded antenna diversity
algorithm
Configurable packet handler
Preamble detector
RX 64 byte FIFO
Low battery detector
Temperature sensor and 8-bit ADC
–40 to +85 °C temperature range
Integrated voltage regulators
Frequency hopping capability
On-chip crystal tuning
20-Pin QFN package
Low BOM
Power-on-reset (POR)
Remote meter reading
Remote keyless entry
Home automation
Industrial control
Sensor networks
Health monitors
Tag readers
®
family includes a complete line of
Patents pending
VDD_RF
S i 4 3 3 0 - B 1
RXp
RXn
NC
NC
Ordering Information:
2
3
4
5
Pin Assignments
1
6
See page 63.
20
7
Si4330
19
GND
8
PAD
18
9
17
10
16
11
15 SCLK
14
13
12
SDI
SDO
VDD_DIG
NC
Si4330

Related parts for SI4330-B1-FMR

SI4330-B1-FMR Summary of contents

Page 1

... Tire pressure monitoring  Wireless PC peripherals Description Silicon Laboratories’ Si4330 is a highly integrated, single chip wireless ISM receiver. The high-performance EZRadioPRO transmitters, receivers, and transceivers allowing the RF system designer to choose the optimal wireless part for their application. The Si4330 offers advanced radio features including continuous frequency coverage from 240– ...

Page 2

... Si4330-B1 Functional Block Diagram 2 Rev 1.0 ...

Page 3

... Synchronization Word Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.9. Receive Header Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1. Modem Settings for FSK and GFSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 8.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 8.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 8.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Rev 1.0 Si4330-B1 Page 3 ...

Page 4

... RSSI and Clear Channel Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 10. Application Notes and Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11. Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12. Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13. Pin Descriptions: Si4330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 14. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 15. Package Markings (Top Marks 15.1. Si4330 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16 ...

Page 5

... Figure 19. General Purpose ADC Architecture ......................................................................... 42 Figure 20. Temperature Ranges using ADC8 ........................................................................... 44 Figure 21. WUT Interrupt and WUT Operation.......................................................................... 47 Figure 22. Low Duty Cycle Mode .............................................................................................. 48 Figure 23. RSSI Value vs. Input Power..................................................................................... 51 Figure 24. Receiver—Schematic Receiver—Top...................................................................... 52 Figure 25. 20-Pin Quad Flat No-Lead (QFN) ............................................................................60 Figure 26. PCB Land Pattern .................................................................................................... 61 Rev 1.0 Si4330-B1 5 ...

Page 6

... Table 11. Frequency Band Selection ....................................................................................... 24 Table 12. Packet Handler Registers ......................................................................................... 35 Table 13. Minimum Receiver Settling Time .............................................................................. 37 Table 14. POR Parameters ...................................................................................................... 40 Table 15. Temperature Sensor Range ..................................................................................... 43 Table 16. Antenna Diversity Control ......................................................................................... 50 Table 17. Register Descriptions ............................................................................................... 54 Table 18. Package Dimensions ................................................................................................ 60 Table 19. PCB Land Pattern Dimensions ................................................................................. 62 1 ...................................................................8 1 .......................................................................9 1 ...................................................................................10 Rev 1.0 Si4330-B1 6 ...

Page 7

... Main Digital Regulator and Temperature Sensor ON, Crystal Oscillator and all other blocks OFF Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF. Crystal Oscillator buffer disabled Synthesizer and regulators enabled Rev 1.0 Si4330-B1 Min Typ Max Units 1.8 3.0 3.6 V — ...

Page 8

... Si4330-B1 Table 2. Synthesizer AC Electrical Characteristics Parameter Symbol Synthesizer Frequency F SYN Range Synthesizer Frequency F RES-LB 2 Resolution F RES-HB Reference Frequency f REF_LV 2 Input Level 2 Synthesizer Settling Time t LOCK 2 F Residual FM RMS 2 Phase Noise L(f M Notes: 1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the " ...

Page 9

... BT = 0.5, channel spacing = 150 kHz Desired Ref Signal 3 dB above sensitivity. Interferer and desired modulated with 40 kbps  kHz GFSK with BT = 0.5 Rejection at the image frequency. IF=937 kHz Measured at RX pins Rev 1.0 Si4330-B1 Min Typ Max Units 240 — 960 MHz — ...

Page 10

... Si4330-B1 Table 4. Auxiliary Block Specifications Parameter Symbol Temperature Sensor TS 2 Accuracy Temperature Sensor TS 2 Sensitivity Low Battery Detector LBD 2 Resolution Low Battery Detector LBD 2 Conversion Time Microcontroller Clock F MC Output Frequency General Purpose ADC ADC 2 Resolution General Purpose ADC Bit ADC ...

Page 11

... DRV<1:0>=LH OmaxLH I DRV<1:0>=HL OmaxHL I DRV<1:0>=HH OmaxHH V I < I source Omax V =1 < I sink Omax V =1 Rev 1.0 Si4330-B1 Min Typ Max Units — — 8 — — 8 — — – 0.6 — — DD — 0.6 –100 — 100 V – 0.6 — — DD — ...

Page 12

... Si4330-B1 Table 7. Absolute Maximum Ratings V to GND DD Voltage on Digital Control Inputs Voltage on Analog Inputs RX Input Power Operating Ambient Temperature Range T Thermal Impedance  JA Junction Temperature T J Storage Temperature Range T STG Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of the specifications is not implied ...

Page 13

... DD  Sensitivity measured at 919 MHz  External reference signal (XOUT) = 1.0 V  Production test schematic (unless noted otherwise)  All RF input and output levels referred to the pins of the Si4330 (not the RF module) Extreme Test Conditions: = –40 to +85 °C   +1.8 to +3.6 VDC DD  ...

Page 14

... Antenna diversity is completely integrated into the Si4330 and can improve the system link budget by 8–10 dB, resulting in substantial range increases depending on the environmental conditions. The Si4330 is designed to work with a microcontroller, crystal, and a few external components to create a very low cost system. Voltage regulators are integrated on-chip which allows for a wide operating supply voltage range from +1 standard 4-pin SPI bus is used to communicate with an external microcontroller. Three configurable general purpose I/Os are available. A complete list of the available GPIO functions is shown in " ...

Page 15

... Depending upon the system communication protocol, an optimal trade-off between the radio wake time and power consumption can be achieved. Table 8 summarizes the operating modes of the Si4330. In general, any given operating mode may be classified as an active mode or a power saving mode. The table indicates which block(s) are enabled (active) in each corresponding mode. With the exception of the SHUTDOWN mode, all can be dynamically selected by sending the appropriate commands over the SPI operating mode. An “ ...

Page 16

... Select high period SW To read back data from the Si4330, the R/W bit must be set to 0 followed by the 7-bit address of the register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored n the SDI pin when R The next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register ...

Page 17

... SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI interface will automatically increment the ADDR and read from/write to the next address. An example burst write transaction is illustrated in Figure 4 and a burst read in Figure 5. As long as nSEL is held low, input data will be latched into the Si4330 every eight SCLK cycles. First Bit RW ...

Page 18

... Si4330-B1 3.2. Operating Mode Control There are three primary states in the Si4330 radio state machine: SHUTDOWN, IDLE, and RX (see Figure 6). The SHUTDOWN state completely shuts down the radio to minimize current consumption. There are five different configurations/options for the IDLE state which can be selected to optimize the chip to the applications needs. ...

Page 19

... This mode of operation is designed for frequency hopping spread spectrum systems (FHSS). TUNE mode is entered by setting pllon = 1 in "Register 07h. Operating Mode and Function Control 1" not necessary to set xton to 1 for this mode, the internal state machine automatically enables the crystal oscillator. Rev 1.0 Si4330-B1 19 ...

Page 20

... Si4330-B1 3.2.3. RX State The RX state may be entered from any of the IDLE modes when the rxon bit is set "Register 07h. Operating Mode and Function Control 1". A built-in sequencer takes care of all the actions required to transition from one of the IDLE modes to the RX state. The following sequence of events will occur automatically to get the chip into RX mode when going from STANDBY mode to RX mode by setting the rxon bit: 1 ...

Page 21

... Interrupts The Si4330 is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers 03h– ...

Page 22

... Si4330-B1 3.4. System Timing The system timing for RX mode is shown in Figure 7. The user only needs to program the desired mode, and the internal sequencer will properly transition the part from its current mode. The VCO will automatically calibrate at every frequency change or power up. The PLL T0 time is to allow for bias settling of the VCO. The PLL TS time is for the settling time of the PLL, which has a default setting of 100 µ ...

Page 23

... Table 11 demonstrates the selection of fb[4:0] for the corresponding frequency band. After selection of the fb (N) the fractional component may be solved with the following equation and fc are the actual numbers stored in the corresponding registers. , must be programmed into the Si4330. Note carrier    MHz ...

Page 24

... Si4330-B1 fb[4:0] Value The chip will automatically shift the frequency of the Synthesizer down by 937.5 kHz (30 MHz ÷ 32) to achieve the correct Intermediate Frequency (IF) when RX mode is entered. Low-side injection is used in the RX Mixing architecture. 24 Table 11. Frequency Band Selection N Frequency Band hbsel=0 24 240–249.9 MHz 25 250– ...

Page 25

... Easy Frequency Programming for FHSS While Registers 73h–77h may be used to program the carrier frequency of the Si4330 often easier to think in terms of “channels” or “channel numbers” rather than an absolute frequency value in Hz. Also, there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is desirable to change frequency by programming a single register. Once the channel step size is set, the frequency may be changed by a single register corresponding to the channel number. A nominal frequency is first set using Registers 73h– ...

Page 26

... Si4330-B1 3.5.4. Frequency Offset Adjustment When the AFC is disabled the frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h not possible to have both AFC and offset as internally they share the same register. The frequency offset adjustment and the AFC both are implemented by shifting the Synthesizer Local Oscillator frequency. This register is a signed register so in order to get a negative offset it is necessary to take the twos complement of the positive offset number ...

Page 27

... AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz The AFC Limiter register is an unsigned register and its value can be obtained from the EZRadioPRO Register Calculator spreadsheet. Frequency Correction AFC disabled Freq Offset Register AFC enabled AFC Rev 1.0 Si4330-B1 27 ...

Page 28

... Si4330-B1 4. Modulation Options 4.1. FIFO Mode In FIFO mode, the receive data is stored in integrated FIFO register memory. The FIFOs are accessed via "Register 7Fh. FIFO Access," and are most efficiently accessed with burst read/write operation as discussed in "3.1. Serial Peripheral Interface (SPI)" on page 16. ...

Page 29

... The received signal strength indicator (RSSI) provides a measure of the signal strength received on the tuned channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel power TM features Rev 1.0 Si4330-B1 29 ...

Page 30

... Si4330-B1 measurements for clear channel assessment (CCA), and carrier sense (CS) functionality. Frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital automatic frequency control (AFC) in receive mode. A comprehensive programmable packet handler including key features of Silicon Labs’ EZMac create a variety of communication topologies ranging from peer-to-peer networks to mesh networks. The extensive programmability of the packet header allows for advanced packet filtering which in turn enables a mix of broadcast, group, and point-to-point communication ...

Page 31

... Crystal Oscillator The Si4330 includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 µs when a suitable parallel resonant crystal is used. The design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components. By default, all that is required off-chip is the 30 MHz crystal ...

Page 32

... Si4330-B1 6. Data Handling and Packet Handler The internal modem is designed to operate with a packet including a 10101... preamble structure. To configure the modem to operate with packet formats without a preamble or other legacy packet structures contact customer support. 6.1. RX FIFO A 64 byte FIFO is integrated into the chip for RX, as shown in Figure 11. "Register 7Fh. FIFO Access" is used to access the FIFO. A burst read, as described in " ...

Page 33

... FIFO, then there are options available for the different fields that will be stored into the FIFO. Figure 15 demonstrates the options and settings available when multiple packets are enabled. Figure 16 demonstrates the operation of fixed packet length and correct/incorrect packets. Data Figure 11. Packet Structure SYNC DATA Rev 1.0 Si4330-B1 CRC Bytes 33 ...

Page 34

... Si4330-B1 Transmission: Register H eader(s) Data Register L ength Data Data FIFO Figure 13. Multiple Packets in RX Packet Handler Initial state FIFO Addr. RX FIFO Addr. Write 0 0 Pointer H L Data 63 63 Figure 14. Multiple Packets in RX with CRC or Header Error 34 RX FIFO Contents: rx_multi_pk_en = 0 rx_multi_pk_en = 1 ...

Page 35

... Rev 1.0 Si4330- POR Def. encrc crc[1] crc[0] crcerror Reserved Reserved hdch[2] hdch[1] hdch[0] synclen[1] synclen[0] prealen[8] prealen[2] prealen[1] prealen[0] Reserved ...

Page 36

... Figure 16. Manchester Coding Example 6.5. Preamble Detector The Si4330 has integrated automatic preamble detection. The preamble length is configurable from 1–256 bytes using the prealen[7:0] field in "Register 33h. Header Control 2" and "Register 34h. Preamble Length," as described in “6.2. Packet Configuration.” The preamble detection threshold, preath[4:0] as set in "Register 35h. Preamble Detection Control 1" ...

Page 37

... Table 13 demonstrates the recommended preamble detection threshold and preamble length for various modes possible to use the Si4330 in a raw mode without the requirement for a 101010 preamble. Contact customer support for further details. ...

Page 38

... Si4330-B1 initiated. The timeout period after preamble detections is defined as the value programmed into the sync word length plus four additional bits. 6.9. Receive Header Check The header check is designed to support 1–4 bytes and broadcast headers. The header length needs to be set in register 33h, hdlen[2:0] ...

Page 39

... The modulation index is equal to 2 times the peak deviation divided by the data rate (Rb). When Manchester coding is disabled, the required channel filter bandwidth is calculated 2Fd + Rb where Fd is the frequency deviation and Rb is the data rate. Rev 1.0 Si4330-B1 39 ...

Page 40

... Auxiliary Functions 8.1. Smart Reset The Si4330 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce a reliable reset signal under any circumstances. Reset will be initiated if any of the following conditions occur:  ...

Page 41

... If the microcontroller clock option is being used there may be the need of a system clock for the microcontroller while the Si4330 is in SLEEP mode. Since the crystal oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This feature is called enable low frequency clock and is enabled by the enlfc bit in “ ...

Page 42

... Si4330-B1 8.3. General Purpose ADC An 8-bit SAR ADC is integrated for general purpose use, as well as for digitizing the on-chip temperature sensor reading. Registers 0Fh "ADC Configuration", 10h "Sensor Offset" and 4Fh "Amplifier Offset" can be used to configure the ADC operation. Every time an ADC conversion is desired, bit 7 "adcstart/adcbusy" in “Register 1Fh. Clock Recovery Gearshift Override” ...

Page 43

... Unit 0 –64 … 64 °C 1 –64 … 192 ° … 128 °C 1 –40 … 216 ° … 341 °K Rev 1.0 Si4330- POR Def. 20h tstrim[2] vbgtrim[1] vbgtrim[0] tvoffs[2] tvoffs[1] tvoffs[0] 00h Slope ADC8 LSB 8 mV/°C 0.5 °C 4 mV/°C 1 °C 8 mV/° ...

Page 44

... Si4330-B1 Temperature Measurement with ADC8 300 250 200 150 100 50 0 -40 -20 Figure 20. Temperature Ranges using ADC8 Temperature [Celsius] Rev 1.0 Sensor Range 0 Sensor Range 1 Sensor Range 2 Sensor Range 3 100 ...

Page 45

... D5 D4 lbdt[ vbat[4] vbat[3] vbat[2] vbat[1] vbat[0]    tage ADCValue ADC Value VDD Voltage [V] 0 < 1.7 1 1.7–1.75 2 1.75–1.8 … … 29 3.1–3.15 30 3.15–3.2 31 > 3.2 Rev 1.0 Si4330- POR Def. lbdt[3] lbdt[2] lbdt[1] lbdt[0] 14h — 45 ...

Page 46

... Si4330-B1 8.6. Wake-Up Timer and 32 kHz Clock Source The chip contains an integrated wake-up timer which can be used to periodically wake the chip from SLEEP mode. The wake-up timer runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in SLEEP mode. If enwt = 1 in "Register 07h. Operating Mode and Function Control 1" when entering SLEEP mode, the wake-up timer will count for a time specified defined in Registers 14– ...

Page 47

... Current Consumption WUT Period GPIOX =00001 nIRQ SPI Interrupt Read Chip State Current Consumption Figure 21. WUT Interrupt and WUT Operation Interrupt Enable enwut =1 ( Reg 06h) Sleep Ready 1 Interrupt Enable enwut =0 ( Reg 06h) Sleep 1 uA Rev 1.0 Si4330-B1 Sleep Ready Sleep 1 ...

Page 48

... Si4330-B1 8.7. Low Duty Cycle Mode The Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is available. The basic operation of the low duty cycle mode is demonstrated in the figure below valid preamble or sync word is not detected the chip will return to sleep mode until the beginning of a new WUT period valid preamble and sync are detected the receiver on period will be extended for the low duty cycle mode duration (TLDC) to receive all of the packet ...

Page 49

... This application uses antenna diversity so a GPIO is used to control the antenna switch. For a complete list of the available GPIO's see “AN4670: Si4330 Register Descriptions.” The GPIO drive strength may be adjusted with the gpioXdrv[1:0] bits. Setting a higher value will increase the drive strength and current capability of the GPIO by changing the driver size ...

Page 50

... Si4330-B1 8.9. Antenna Diversity To mitigate the problem of frequency-selective fading due to multi-path propagation, some radio systems use a scheme known as antenna diversity. In this scheme, two antennas are used. Each time the radio enters RX mode the receive signal strength from each antenna is evaluated. This evaluation process takes place during the preamble portion of the packet ...

Page 51

... Figure 23. RSSI Value vs. Input Power rssi[7] rssi[6] rssi[5] rssi[4] rssith[7] rssith[6] rssith[5] rssith[4] rssith[3] RSSI vs Input Power -80 -60 -40 In Pow [dBm] Rev 1.0 Si4330- POR Def. rssi[3] rssi[2] rssi[1] rssi[0] — rssith[2] rssith[1] rssith[0] 00h - ...

Page 52

... Si4330-B1 9. Reference Design Reference designs are available at schematics, BOM, and layout. RX matching component values for different frequency bands can be found in “AN427: EZRadioPRO Si433x and Si443x RX LNA Matching.” 52 www.silabs.com for many common applications which include recommended Rev 1.0 ...

Page 53

... AN463: Support for Non-Standard Packet Structures and RAW Mode  AN466: Si4030/31/32 Register Descriptions  AN467: Si4330 Register Descriptions 11. Customer Support Technical support for the complete family of Silicon Labs wireless products is available by accessing the wireless section of the Silicon Labs' website at www.silabs.com\wireless. For answers to common questions please visit the wireless knowledge base at www ...

Page 54

... Si4330-B1 12. Register Table and Descriptions Add R/W Function/Desc 01 R Device Version 02 R Device Status 03 R Interrupt Status Interrupt Status 2 05 R/W Interrupt Enable 1 06 R/W Interrupt Enable 2 07 R/W Operating & Function Control 1 08 R/W Operating & Function Control 2 09 R/W ...

Page 55

... Reserved sgi agcen lnagain Reserved Reserved Reserved enphpwdn trclk[1] trclk[0] dtmod[1] dtmod[0] fo[7] fo[6] fo[5] fo[4] Reserved Reserved Reserved Reserved Rev 1.0 Si4330-B1 Data adrssia[3] adrssia[2] adrssia[1] adrssia[0] adrssib[3] adrssib[2] adrssib[1] adrssib[0] Afclim[3] Afclim[2] Afclim[1] Afclim[0] afc_corr[5] afc_corr[4] afc_corr[3] afc_corr[2] madeten ...

Page 56

... R/W Frequency Hopping Channel Select 7A R/W Frequency Hopping Step Size 7B 7E R/W RX FIFO Control Reserved 7F R/W FIFO Access Note: Detailed register descriptions are available in “AN467: Si4330 Register Descriptions.” sbsel hbsel fb[4] fc[15] fc[14] fc[13] fc[12] fc[7] fc[6] fc[5] fc[4] ...

Page 57

... PKG PADDLE_GND GND The exposed metal paddle on the bottom of the Si4330 supplies the RF and circuit ground(s) for the entire chip very important that a good solder connection is made between this exposed metal paddle and the ground plane of the PCB underlying the Si4330. ...

Page 58

... Si4330-B1 14. Ordering Information Part Number* Si4330-B1-FM ISM EZRadioPRO Receiver *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. 58 Description Rev 1.0 Package Operating Type Temperature QFN-20 – °C Pb-free ...

Page 59

... Package Markings (Top Marks) 15.1. Si4330 Top Mark 15.2. Top Mark Explanation Mark Method: YAG Laser Line 1 Marking Part Number Line 2 Marking Die Revision TTTTT = Internal Code Line 3 Marking: YY= Year WW = Workweek 0 = Si4330 B = Revision B1 Internal tracking code. Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date ...

Page 60

... Si4330-B1 16. Package Outline: Si4330 Figure 25 illustrates the package details for the Si4330. Table 23 lists the values for the dimensions shown in the illustration. Figure 25. 20-Pin Quad Flat No-Lead (QFN) Symbol aaa bbb ccc ddd eee Notes: 1. All dimensions are shown in millimeters (mm) unless otherwise noted. ...

Page 61

... PCB Land Pattern: Si4330 Figure 26 illustrates the PCB land pattern details for the Si4330. Table 24 lists the values for the dimensions shown in the illustration. Figure 26. PCB Land Pattern Rev 1.0 Si4330-B1 61 ...

Page 62

... Si4330-B1 Table 19. PCB Land Pattern Dimensions Symbol Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on IPC-7351 guidelines. Note: Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad µm minimum, all the way around the pad ...

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... Updated descriptions on FIFO and Direct Modes  Changed pin and pin 6 to Ant1  Updated "9. Reference Design" on page 52.  Moved Detailed Register Descriptions to Application Note (AN440)  Moved Measurement Results to Application Note (AN438)  Replaced Applications Section with links to App Notes Rev 1.0 Si4330-B1 63 ...

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... Si4330- ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...

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