SI4704-C40-GM Silicon Laboratories Inc, SI4704-C40-GM Datasheet
SI4704-C40-GM
Specifications of SI4704-C40-GM
Available stocks
Related parts for SI4704-C40-GM
SI4704-C40-GM Summary of contents
Page 1
... Table and portable radios Stereos Mini/micro systems CD/DVD players Boom boxes Description The Si4704/05 integrates all functions required for an advanced broadcast FM radio receiver, from antenna input to stereo audio output. Functional Block Diagram FM Antenna FMI LNA RFGND AGC LPI 0/90 32 ...
Page 2
... Si4704/05-C40 2 Rev. 1.0 ...
Page 3
... Pin Descriptions: Si4704/05- Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8. Package Markings (Top Marks 8.1. Si4704 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2. Si4705 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9. Package Outline: Si4704/05- 10. PCB Land Pattern: Si4704/05-C40- 11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Si4704/05-C40 Rev. 1.0 Page ...
Page 4
... Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. The Si4704/05 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < HBM. Handling and assembly of these devices should be done only at ESD-protected workstations. ...
Page 5
... Low SNR level DDPD I SCLK, RCLK inactive IOPD 500 µA 0 OUT –500 µA OL OUT Rev. 1.0 Si4704/05-C40 Min Typ Max Unit — 19 — 19 — 19 — 320 600 µA — — µA — 0 –0.3 — 0 –10 — 10 µA –10 — ...
Page 6
... Si4704/05-C40 Table 4. Reset Timing Characteristics (V = 2 1. Parameter RST Pulse Width and GPO1, GPO2/INT Setup to RST GPO1, GPO2/INT Hold from RST Important Notes: 1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST ...
Page 7
... RST. 3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 4. The Si4704/05 delays SDIO by a minimum of 300 ns from the V t specification. ...
Page 8
... Si4704/05-C40 SU:STA HD:STA LOW 70% SCLK 30% 70% SDIO 30% START t r:IN Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, SDIO R/W START ADDRESS + R/W Figure 3. 2-Wire Control Interface Read and Write Timing Diagram HIGH t r:IN f: HD:DAT SU:DAT D7-D0 ACK DATA ACK Rev ...
Page 9
... HSDIO HIGH LOW t S A6-A5, R/W, A0 D15 A4-A1 Address HSDIO CDV t S A6-A5, R/W, A0 D15 A4-A1 Address In ½ Cycle Bus Turnaround Rev. 1.0 Si4704/05-C40 Min Typ Max Unit 0 — 2.5 MHz 25 — — — — — — — — — — ...
Page 10
... Si4704/05-C40 Table 7. SPI Control Interface Characteristics (V = 2 1. Parameter SCLK Frequency SCLK High Time SCLK Low Time SDIO Input, SEN to SCLKSetup SDIO Input to SCLKHold Hold SEN Input to SCLK to SDIO Output Valid SCLK ...
Page 11
... Figure 8. Digital Audio Interface Timing Parameters – °C) A Symbol Test Condition t DCT t DCH t DCL t SU:DFS t HD:DFS t PD:DOUT t DCL t DCT t HD:DFS PD:OUT Rev. 1.0 Si4704/05-C40 Min Typ Max 26 — 1000 10 — — 10 — — 5 — — 5 — — 0 — SU:DFS 2 S Mode ...
Page 12
... Si4704/05-C40 Table 9. FM Receiver Characteristics (V = 2 1. Parameter Input Frequency Sensitivity with Headphone 3,4,5 Network Sensitivity with 50 Network 3,4,5,6 6 RDS Sensitivity 6 LPI Sensitivity 6,7 LNA Input Resistance 6,7 LNA Input Capacitance 6,8 Input IP3 3,4,6,7 AM Suppression Adjacent Channel Selectivity ...
Page 13
... MHz, ±8 MHz FM_DEEMPHASIS = 2 FM_DEEMPHASIS = 1 R Single-ended L C Single-ended L RCLK tolerance = 100 ppm From powerdown Input levels of 8 and 60 dBµ Input . AGC is disabled. Rev. 1.0 Si4704/05-C40 Min Typ Max Unit — 40 — dBµV — 35 — dBµV — 0.1 0.5 % ...
Page 14
... Si4704/05-C40 Table 10. 64–75.9 MHz Input Frequency FM Receiver Characteristics (V = 2 1. Parameter Input Frequency Sensitivity with Headphone 3,4,5 Network 7 LNA Input Resistance 7 LNA Input Capacitance 8 Input IP3 3,4,7 AM Suppression Adjacent Channel Selectivity Alternate Channel Selectivity 3,4,7 Audio Output Voltage ...
Page 15
... Crystal Frequency Tolerance Board Capacitance Notes: 1. The Si4704/05 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies between 31.130 kHz and 40 MHz that are not supported. See “AN332: Si47xx Programming Guide,” Table 6 for more details. ± frequency tolerance of 50 ppm is required for FM seek/tune using 50 kHz channel spacing. = – ...
Page 16
... Layout, and Design Guidelines” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 5. Pin 2 or Pin 4 connects to the FM antenna interface. Pin 2 is for a headphone antenna. Pin 4 is for an integrated antenna. 6. Place Si4704/05 as close as possible to antenna and keep the FMI and LPI traces as short as possible ...
Page 17
... Bill of Materials Component(s) C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R U1 Si4704/05 FM Radio Receiver C2, C3 Crystal load capacitors, 22 pF, ±5%, COG (Optional: for crystal oscillator option) X1 32.768 kHz crystal (Optional: for crystal oscillator option) R1 Resistor, 2 k(Optional: for digital audio) R2 Resistor, 2 k(Optional: for digital audio) Resistor, 600 ...
Page 18
... PCB trace or wire antenna input, and a that may be integrated into the system enclosure. There is a clocking mode to choose to clock the Si4704/05 from a reference clock or crystal. On the Si4705, there is an audio output mode to choose between an analog and/or digital audio output. Rev. 1.0 ...
Page 19
... DACs and ADCs on the audio baseband processor. The Si4704/05 is reset by applying a logic low on RST signal. This causes all register values to be reset to their default values. The digital output interface supply (V provides voltage to the RST, SEN, SDIO, RCLK, DOUT, ...
Page 20
... Si4704/05-C40 INVERTED (OFALL = 1) DCLK (OFALL = 0) DCLK DFS (OMODE = 0000) 1 DCLK DOUT 1 2 MSB INVERTED (OFALL = 1) DCLK (OFALL = 0) DCLK DFS Left-Justified (OMODE = 0110) DOUT 1 2 MSB Figure 11. Left-Justified Digital Audio Format (OFALL = 0) DCLK DFS DOUT 1 (OMODE = 1100) st (MSB at 1 rising edge) MSB ...
Page 21
... FM receivers by reducing the effects of high-frequency interference and noise. When the FM signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. The Si4704/05 incorporates a de-emphasis filter which attenuates high frequencies to restore a flat frequency response. Two time constants are used in various regions. The de- emphasis time constant is programmable µ ...
Page 22
... The serial port can operate in three bus modes: 2-wire mode, 3-wire mode, or SPI mode. The Si4704/05 selects the bus mode by sampling the state of the GPO1 and GPO2 pins on the rising edge of RST. The GPO1 pin includes ...
Page 23
... SCLK. For read operations, the control word is followed by a delay of one-half SCLK cycle for bus turn-around. Next, the Si4704/05 will drive the 16-bit read data word serially on SDIO, changing the state of SDIO on each rising edge of SCLK. A transaction ends when the user sets SEN high, then pulses SCLK high and low one final time ...
Page 24
... Arguments are specific to a given command and are used to modify the command. A partial list of commands is available in Table 13, “Selected Si4704/05 Commands,” on page 25. Properties are a special command argument used to modify the default chip operation and are generally configured immediately after powerup ...
Page 25
... Commands and Properties Table 13. Selected Si4704/05 Commands Cmd Name 0x01 POWER_UP 0x10 GET_REV 0x11 POWER_DOWN 0x12 SET_PROPERTY 0x13 GET_PROPERTY 0x20 FM_TUNE_FREQ 0x21 FM_SEEK_START 0x22 FM_TUNE_STATUS 0x23 FM_RSQ_STATUS 0x24 FM_RDS_STATUS Description Powerup device and mode selection. Modes include analog or digital output and reference clock or crystal support. ...
Page 26
... Si4704/05-C40 Table 14. Selected Si4704/05 Properties Prop Name 0x1100 FM_DEEMPHASIS FM_BLEND_STEREO_ 0x1105 THRESHOLD FM_BLEND_MONO_ 0x1106 THRESHOLD FM_RSQ_INT_ 0x1200 SOURCE FM_SOFT_MUTE_ 0x1302 MAX_ATTENUATION FM_SEEK_BAND_ 0x1400 BOTTOM 0x1401 FM_SEEK_BAND_TOP FM_SEEK_FREQ_ 0x1402 SPACING FM_SEEK_TUNE_ 0x1403 SNR_THRESHOLD FM_SEEK_TUNE_ 0x1404 RSSI_TRESHOLD 0x1500 RDS_INT_SOURCE 0x1501 RDS_INT_FIFO_COUNT 0x1502 RDS_CONFIG ...
Page 27
... Pin Descriptions: Si4704/05-GM RFGND Pin Number(s) Name FMI 3 RFGND 4 LPI 5 RST 6 SEN 7 SCLK 8 SDIO 9 RCLK 12, GND PAD GND 13 ROUT 14 LOUT 15 DOUT 16 DFS 17 GPO3/DCLK 18 GPO2/INT 19 GPO1 FMI 2 15 DOUT 3 14 LOUT GND PAD LPI 4 13 ROUT RST 5 12 GND 6 11 VDD Description No connect ...
Page 28
... Si4704/05-C40 7. Ordering Guide Part Number* Si4704-C40-GM FM Broadcast Radio Receiver Si4705-C40-GM FM Broadcast Radio Receiver with RDS/RBDS *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. 28 Description Rev. 1.0 Package Operating Type Temperature QFN – ...
Page 29
... Line 2 Marking Die Revision TTT = Internal Code Line 3 Marking: Circle = 0.5 mm Diameter (Bottom-Left Justified Year WW = Workweek 0440 CTTT YWW Figure 14. Si4704 Top Mark 0540 CTTT YWW Figure 15. Si4705 Top Mark 04 = Si4704 05 = Si4705 40 = Firmware Revision 4 Revision C Die. Internal tracking code. Pin 1 Identifier. ...
Page 30
... Si4704/05-C40 9. Package Outline: Si4704/05-GM Figure 16 illustrates the package details for the Si4704/05. Table 15 lists the values for the dimensions shown in the illustration. Figure 16. 20-Pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A 0.50 0.55 A1 0.00 0.02 b 0.20 0.25 c 0.27 0.32 D 3.00 BSC D2 1 ...
Page 31
... PCB Land Pattern: Si4704/05-C40-GM Figure 17 illustrates the PCB land pattern details for the Si4704/05-GM. Table 16 lists the values for the dimensions shown in the illustration. Figure 17. PCB Land Pattern Rev. 1.0 Si4704/05-C40 31 ...
Page 32
... Si4704/05-C40 Table 16. PCB Land Pattern Dimensions Symbol Millimeters Min 2.10 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0 ...
Page 33
... Contact your local sales representatives for more information or to obtain copies of the following references: EN55020 Compliance Test Certificate AN332: Si47xx Programming Guide AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure Si4704/05-C40 Rev. 1.0 33 ...
Page 34
... Si4704/05-C40 OCUMENT HANGE IST Revision 0.7 to Revision 0.71 V minimum changed from 1 1. Revision 0.71 to Revision 1.0 Updated patent information on page 1. Updated Table 3 on page 5. 34 Rev. 1.0 ...
Page 35
... N : OTES Si4704/05-C40 Rev. 1.0 35 ...
Page 36
... Si4704/05-C40 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: FMinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...