SI4730-C40-GMR Silicon Laboratories Inc, SI4730-C40-GMR Datasheet
SI4730-C40-GMR
Specifications of SI4730-C40-GMR
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SI4730-C40-GMR Summary of contents
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... Table and portable radios Stereos Mini/micro systems CD/DVD players Boom boxes Description The Si4730/31 is the first digital CMOS AM/FM radio receiver IC that integrates the complete tuner function from antenna input to audio output. Functional Block Diagram AMI AM LNA ANT RFGND AGC FM ...
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... Si4730/31-C40 2 Rev. 1.0 ...
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... Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10. Package Markings (Top Marks 10.1. Si4730/31 Top Mark (QFN 10.2. Top Mark Explanation (QFN 10.3. Si4730/31 Top Mark (SSOP 10.4. Top Mark Explanation (SSOP 11. Package Outline: Si4730/31 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 12. PCB Land Pattern: Si4730/31 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 13. Package Outline: Si4730/31 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14 ...
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... Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. The Si4730/31 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < HBM. Handling and assembly of these devices should only be done at ESD-protected workstations. ...
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... I Analog Output Mode DDPD I SCLK, RCLK inactive IOPD 500 µA 0 OUT –500 µA OL OUT Rev. 1.0 Si4730/31-C40 Min Typ Max Unit — 19 — 19 — 19 — 15.4 20.5 mA — 320 600 µA — — µA — 0 –0.3 — 0 –10 — ...
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... Si4730/31-C40 Table 4. Reset Timing Characteristics (V = 2 1. Parameter RST Pulse Width and GPO1, GPO2/INT Setup to RST GPO1, GPO2/INT Hold from RST Important Notes: 1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST ...
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... RST. 3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 4. The Si4730/31 delays SDIO by a minimum of 300 ns from the V t specification. ...
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... Si4730/31-C40 SU:STA HD:STA LOW 70% SCLK 30% 70% SDIO 30% START t r:IN Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, SDIO R/W START ADDRESS + R/W Figure 3. 2-Wire Control Interface Read and Write Timing Diagram HIGH t r:IN f: HD:DAT SU:DAT D7-D0 ACK DATA ACK Rev ...
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... HSDIO HIGH LOW t S A6-A5, R/W, A0 D15 A4-A1 Address HSDIO CDV t S A6-A5, R/W, A0 D15 A4-A1 ½ Cycle Bus Address In Turnaround Rev. 1.0 Si4730/31-C40 Min Typ Max Unit 0 — 2.5 MHz 25 — — — — — — — — — — ...
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... Si4730/31-C40 Table 7. SPI Control Interface Characteristics (V = 2 1. Parameter SCLK Frequency SCLK High Time SCLK Low Time SDIO Input, SEN to SCLKSetup SDIO Input to SCLKHold Hold SEN Input to SCLK to SDIO Output Valid SCLK ...
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... Figure 8. Digital Audio Interface Timing Parameters – °C) A Symbol Test Condition t DCT t DCH t DCL t SU:DFS t HD:DFS t PD:DOUT t DCL t DCT t HD:DFS PD:OUT Rev. 1.0 Si4730/31-C40 Min Typ Max 26 — 1000 10 — — 10 — — 5 — — 5 — — 0 — SU:DFS 2 S Mode ...
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... Si4730/31-C40 Table 9. FM Receiver Characteristics (V = 2 1. Parameter Input Frequency Sensitivity with Headphone 3,4,5 Network Sensitivity with 50 Network 3,4,5,6 6 RDS Sensitivity 6,7 LNA Input Resistance 6,7 LNA Input Capacitance 6,8 Input IP3 3,4,6,7 AM Suppression Adjacent Channel Selectivity Alternate Channel Selectivity ...
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... MHz, ±8 MHz R Single-ended L C Single-ended L RCLK tolerance = 100 ppm From powerdown Input levels of 8 and 60 dBµ Input . AGC is disabled. Rev. 1.0 Si4730/31-C40 Min Typ Max Unit — 32 — dBµV — 38 — dBµV — 40 — ...
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... Si4730/31-C40 Table 10. 64–75.9 MHz Input Frequency FM Receiver Characteristics (V = 2 1. Parameter Input Frequency Sensitivity with Headphone 3,4,5 Network 7 LNA Input Resistance 7 LNA Input Capacitance 8 Input IP3 3,4,7 AM Suppression Adjacent Channel Selectivity Alternate Channel Selectivity 3,4,7 Audio Output Voltage ...
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... Stray capacitance on antenna and board must be < achieve full tuning range at higher inductance levels. 1,2 Test Condition f RF (S+N)/ THD < 8% ΔV = 100 mV , 100 Hz DD RMS From powerdown Rev. 1.0 Si4730/31-C40 Min Typ Max Unit 520 — 1710 kHz — µV EMF — ...
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... Crystal Frequency Tolerance Board Capacitance Notes: 1. The Si4730/31 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies between 31.130 kHz and 40 MHz that are not supported. For more details, see Table 6 of “AN332: Si47xx Programming Guide” frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing. ...
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... To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface. 6. Place Si4730/31 as close as possible to antenna and keep the FMI and AMI traces as short as possible ...
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... To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 6. Pin 8 connects to the FM antenna interface, and pin 12 connects to the AM antenna interface. 7. Place Si4730/31 as close as possible to antenna and keep the FMI and AMI traces as short as possible ...
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... C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R C5 Coupling capacitor, 0.47 µF, ±20%, Z5U/X7R L1 Ferrite loop stick, 180 U1 Si4730/31 AM/FM Radio Tuner T1 Transformer, 1–5 turns ratio L2 Air loop antenna, 10–20 µH C2, C3 Crystal load capacitors, 22 pF, ±5%, COG (Optional for crystal oscillator option) ...
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... In AM mode, radio signals are received on AMI and processed by the AM front-end circuitry. In addition to the receiver mode, there is a clocking mode to choose to clock the Si4730/31 from a reference clock or crystal. On the Si4731, there is an audio output mode to choose between an analog and/or digital audio output. ...
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... The receiver mode and the audio output mode are set by the POWER_UP command listed in Table 14, “Selected Si473x Commands,” on page 26. 5.3. FM Receiver The Si4730/31 FM receiver is based on the proven Si4700/01 FM tuner. The receiver uses a digital low-IF architecture allowing the elimination components and factory adjustments ...
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... LSB Figure 12. DSP Digital Audio Format 5.6.1. Stereo Decoder The Si4730/31's automatically decodes the MPX signal using DSP techniques. The kHz (L+R) signal is the mono output of the FM tuner. Stereo is generated from the (L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is used as a reference to recover the (L– ...
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... The serial port can operate in three bus modes: 2-wire mode, 3-wire mode, or SPI mode. The Si4730/31 selects the bus mode by sampling the state of the GPO1 and GPO2 pins on the rising edge of RST. The GPO1 pin includes an internal pull-up resistor, which is connected while Rev ...
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... SCLK. For read operations, the control word is followed by a delay of one-half SCLK cycle for bus turn-around. Next, the Si4730/31 will drive the 16-bit read data word serially on SDIO, changing the state of SDIO on each rising edge of SCLK. A transaction ends when the user sets SEN high, then pulses SCLK high and low one final time ...
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... Responses provide the user information and are echoed after a command and associated arguments are issued. All commands provide a 1-byte status update, indicating interrupt and clear-to-send status information. For a detailed description of the commands and properties for the Si4730/31, see “AN332: Si47xx Programming Guide.” Rev. 1.0 25 ...
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... Si4730/31-C40 6. Commands and Properties Table 14. Selected Si473x Commands Cmd Name 0x01 POWER_UP 0x10 GET_REV 0x11 POWER_DOWN 0x12 SET_PROPERTY 0x13 GET_PROPERTY 0x20 FM_TUNE_FREQ 0x21 FM_SEEK_START 0x23 FM_RSQ_STATUS 0x24 FM_RDS_STATUS 0x40 AM_TUNE_FREQ 0x41 AM_SEEK_START 0x43 AM_RSQ_STATUS 26 Description Powerup device and mode selection. Modes include receive, analog or digital output, and reference clock or crystal support ...
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... Sets the rate of attack when entering or leaving soft mute. The default is 278 dB/s. Sets maximum attenuation during soft mute (dB). Sets SNR threshold to engage soft mute. Default is 0 dB, which disables soft mute. Sets the bottom of the AM band for seek. Default is 520. Rev. 1.0 Si4730/31-C40 Default 0x0002 0x0031 0x001E 0x0000 0x0040 ...
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... Si4730/31-C40 Table 15. Selected Si473x Properties (Continued) Prop Name 0x3401 AM_SEEK_BAND_TOP AM_SEEK_FREQ_ 0x3402 SPACING AM_SEEK_SNR_ 0x3403 THRESHOLD AM_SEEK_RSSI_ 0x3404 THRESHOLD 0x4000 RX_VOLUME 0x4001 RX_HARD_MUTE 28 Description Sets the top of the AM band for seek. Selects frequency spacing for AM seek. Default is 10 kHz spacing. Sets the SNR threshold for a valid AM Seek/Tune. If the value is zero, then SNR threshold is not considered when doing a seek ...
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... Pin Descriptions: Si4730/31-GM RFGND Pin Number(s) Name connect. Leave floating. 2 FMI FM RF inputs. FMI should be connected to the antenna trace. 3 RFGND RF ground. Connect to ground plane on PCB. 4 AMI AM RF input. AMI should be connected to the AM antenna. 5 RST Device reset (active low) input. 6 SEN Serial enable input (active low). ...
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... Si4730/31-C40 8. Pin Descriptions: Si4730/31-GU Pin Number(s) Name 1 DOUT Digital output data in digital output mode. 2 DFS Digital frame synchronization input in digital output mode. 3 GPO3/DCLK General purpose output, crystal oscillator, or digital bit synchronous clock input in digital output mode. 4 GPO2/INT General purpose output or interrupt pin. ...
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... Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. SSOP devices operate down °C. DD Description Package Pb-free Pb-free Pb-free Pb-free Rev. 1.0 Si4730/31-C40 Operating Type Temperature/Voltage QFN – °C 2.7 to 5.5 V SSOP – °C 2.0 to 5.5 V QFN – ...
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... Line 3 Marking: Circle = 0.5 mm Diameter (Bottom-Left Justified Year WW = Workweek 32 3140 CTTT YWW 30 = Si4730 Si4731 Firmware Revision 4. Revision C Die. Internal tracking code. Pin 1 Identifier. Assigned by the Assembly House. Corresponds to the last significant digit of the year and work week of the mold date. Rev. 1.0 ...
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... Top Mark Explanation (SSOP) Mark Method: YAG Laser Part Number Line 1 Marking: Die Revision Firmware Revision YY = Year Line 2 Marking Work week TTTTTT = Manufacturing code 4730C40GU YYWWTTTTTT 4730 = Si4730; 4731 = Si4731 Revision C die Firmware Revision 4.0. Assigned by the Assembly House. Rev. 1.0 Si4730/31-C40 33 ...
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... Si4730/31-C40 11. Package Outline: Si4730/31 QFN Figure 14 illustrates the package details for the Si4730/31. Table 16 lists the values for the dimensions shown in the illustration. Figure 14. 20-Pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A 0.50 0.55 A1 0.00 0.02 b 0.20 0.25 c 0.27 0. ...
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... PCB Land Pattern: Si4730/31 QFN Figure 15 illustrates the PCB land pattern details for the Si4730/31-C40-GM QFN. Table 17 lists the values for the dimensions shown in the illustration. Figure 15. PCB Land Pattern Rev. 1.0 Si4730/31-C40 35 ...
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... Si4730/31-C40 Table 17. PCB Land Pattern Dimensions Symbol Millimeters Min 2.10 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0 ...
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... Package Outline: Si4730/31 SSOP Figure 16 illustrates the package details for the Si4730/31. Table 18 lists the values for the dimensions shown in the illustration. Dimension θ aaa bbb ccc ddd Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. ...
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... Si4730/31-C40 14. PCB Land Pattern: Si4730/31 SSOP Figure 17 illustrates the PCB land pattern details for the Si4730/31-C40-GU SSOP. Table 19 lists the values for the dimensions shown in the illustration. Table 19. PCB Land Pattern Dimensions Dimension General: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...
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... Contact your local sales representatives for more information or to obtain copies of the following references: EN55020 Compliance Test Certificate AN332: Si47xx Programming Guide AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure Si4730/31-C40 Rev. 1.0 39 ...
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... Updated Table 9 on page 12. Updated Table 11 on page 15. Updated "3. Typical Application Schematic (SSOP)" on page 18. Updated "4. Bill of Materials (QFN/SSOP)" on page 19. Updated "8. Pin Descriptions: Si4730/31-GU" on page 30. Updated "9. Ordering Guide" on page 31. 40 1,2 ,” Rev. 1.0 ...
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... N : OTES Si4730/31-C40 Rev. 1.0 41 ...
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... Si4730/31-C40 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: FMinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...