SI4734-C40-GM Silicon Laboratories Inc, SI4734-C40-GM Datasheet

no-image

SI4734-C40-GM

Manufacturer Part Number
SI4734-C40-GM
Description
IC RX AM/FM/SW/LW RADIO 20UQFN
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI4734-C40-GM

Frequency
153kHz ~ 279kHz, 520kHz ~ 1.71MHz, 2.3MHz ~ 26.1MHz, 64MHz ~ 108MHz
Modulation Or Protocol
AM, FM, SW-LW
Applications
General Purpose
Current - Receiving
19.9mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Features
RSSI Equipped
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-20°C ~ 85°C
Package / Case
20-UQFN, 20-µQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Sensitivity
-
Memory Size
-
Data Rate - Maximum
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
B
Features
Applications
Description
The Si4734/35 is the first digital CMOS AM/FM radio receiver IC that integrates
the complete tuner function from antenna input to audio output.
Functional Block Diagram
Rev. 1.0 12/09
Worldwide FM band support
(64–108 MHz)
Worldwide AM band support
(520–1710 kHz)
SW band support
(2.3–26.1 MHz)
LW band support
(153–279 kHz)
Excellent real-world performance
Freq synthesizer with integrated VCO
Advanced seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Digital FM stereo decoder
Programmable AVC max gain
Programmable de-emphasis
Seven selectable AM channel filters
Table and portable radios
Stereos
Mini/micro systems
CD/DVD players
Boom boxes
ROADCAST
2.0–5.5 V (SSOP)
2.7–5.5 V (QFN)
AM / LW
ANT
FM / SW
ANT
RFGND
GND
VDD
AMI
FMI
LNA
LNA
AGC
AGC
LDO
AM/FM R
Copyright © 2009 by Silicon Laboratories
AFC
AM/FM/SW/LW digital tuning
EN55020 compliant
No manual alignment necessary
Programmable reference clock
Volume control
Adjustable soft mute control
RDS/RBDS processor (Si4735)
Optional digital audio out (Si4735)
2-wire and 3-wire control interface
Integrated LDO regulator
2.0 to 5.5 V supply voltage (SSOP)
2.7 to 5.5 V supply voltage (QFN)
Wide range of ferrite loop sticks and
air loop antennas supported
QFN and SSOP packages
ADC
ADC
Modules
Clock radios
Mini HiFi
Entertainment systems
RoHS compliant
(Si4735)
LOW-IF
ADIO
RDS
DSP
INTERFACE
Si4734/35
CONTROL
DIGITAL
(Si4735)
AUDIO
DAC
DAC
R
GPO/DCLK
ECEIVER
DOUT
ROUT
LOUT
VIO
1.85-3.6 V
DFS
S i 4 7 3 4 / 3 5 - C 4 0
This product, its features, and/or its
architecture is covered by one or more of
the following patents, as well as other
patents, pending and issued, both foreign
and
7,272,375;
7,426,376;
7,339,504.
RFGND
GPO3/DCLK
GPO2/INT
domestic:
RST
AMI
FMI
NC
RFGND
Ordering Information:
DOUT
GPO1
DFS
FMI
AMI
Si4734/35 (SSOP)
NC
NC
NC
NC
Pin Assignments
2
3
4
5
Si4734/35 (QFN)
1
6
See page 32.
20
7
7,321,324;
7,471,940;
10
11
12
1
2
3
4
5
6
7
8
9
7,127,217;
19
8
GND
PAD
18
9
17
10
Si4734/35-C40
24
23
22
21
20
19
18
17
16
15
14
13
16
11
15 DOUT
14
13
12
7,272,373;
7,355,476;
7,339,503;
ROUT
DBYP
VDD
LOUT
VIO
RCLK
SDIO
SCLK
SEN
RST
GND
GND
LOUT
ROUT
GND
VDD

Related parts for SI4734-C40-GM

SI4734-C40-GM Summary of contents

Page 1

... Table and portable radios  Stereos  Mini/micro systems  CD/DVD players  Boom boxes Description The Si4734/35 is the first digital CMOS AM/FM radio receiver IC that integrates the complete tuner function from antenna input to audio output. Functional Block Diagram ANT FMI LNA AGC AMI ...

Page 2

... Si4734/35-C40 2 Rev. 1.0 ...

Page 3

... Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10. Package Markings (Top Marks 10.1. Si4734/35 Top Mark (QFN 10.2. Top Mark Explanation (QFN 10.3. Si4734/35 Top Mark (SSOP 10.4. Top Mark Explanation (SSOP 11. Package Outline: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12. PCB Land Pattern: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13. Package Outline: Si4734/35 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 14 ...

Page 4

... Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. The Si4734/35 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < HBM. Handling and assembly of these devices should only be done at ESD-protected workstations. ...

Page 5

... I Analog Output Mode DDPD I SCLK, RCLK inactive IOPD 500 µA 0 OUT –500 µA OL OUT Rev. 1.0 Si4734/35-C40 Min Typ Max Unit — 19 — 19 — 19 — 15.4 20.5 mA — 320 600 µA — — µA — 0 –0.3 — 0 –10 — ...

Page 6

... Si4734/35-C40 Table 4. Reset Timing Characteristics (V = 2 1. Parameter RST Pulse Width and GPO1, GPO2/INT Setup to RST GPO1, GPO2/INT Hold from RST Important Notes: 1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST ...

Page 7

... RST. 3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 4. The Si4734/35 delays SDIO by a minimum of 300 ns from the V t specification. ...

Page 8

... Si4734/35-C40 SU:STA HD:STA LOW 70% SCLK 30% 70% SDIO 30% START t r:IN Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, SDIO R/W START ADDRESS + R/W Figure 3. 2-Wire Control Interface Read and Write Timing Diagram HIGH t r:IN f: HD:DAT SU:DAT D7-D0 ACK DATA ACK Rev ...

Page 9

... HSDIO HIGH LOW t S A6-A5, R/W, A0 D15 A4-A1 Address HSDIO CDV t S A6-A5, R/W, A0 D15 A4-A1 ½ Cycle Bus Address In Turnaround Rev. 1.0 Si4734/35-C40 Min Typ Max Unit 0 — 2.5 MHz 25 — — — — — — — — — — ...

Page 10

... Si4734/35-C40 Table 7. SPI Control Interface Characteristics (V = 2 1. Parameter SCLK Frequency SCLK High Time SCLK Low Time SDIO Input, SEN to SCLKSetup SDIO Input to SCLKHold  Hold SEN Input to SCLK  to SDIO Output Valid SCLK  ...

Page 11

... Figure 8. Digital Audio Interface Timing Parameters – °C) A Symbol Test Condition t DCT t DCH t DCL t SU:DFS t HD:DFS t PD:DOUT t DCL t DCT t HD:DFS PD:OUT Rev. 1.0 Si4734/35-C40 Min Typ Max 26 — 1000 10 — — 10 — — 5 — — 5 — — 0 — SU:DFS 2 S Mode ...

Page 12

... Si4734/35-C40 Table 9. FM Receiver Characteristics (V = 2 1. Parameter Input Frequency Sensitivity with Headphone 3,4,5 Network Sensitivity with 50  Network 3,4,5,6 6 RDS Sensitivity 6,7 LNA Input Resistance 6,7 LNA Input Capacitance 6,8 Input IP3 3,4,6,7 AM Suppression Adjacent Channel Selectivity Alternate Channel Selectivity ...

Page 13

... MHz, ±8 MHz R Single-ended L C Single-ended L RCLK tolerance = 100 ppm From powerdown Input levels of 8 and 60 dBµ Input . AGC is disabled. Rev. 1.0 Si4734/35-C40 Min Typ Max Unit — 32 — dBµV — 38 — dBµV — 40 — ...

Page 14

... Si4734/35-C40 Table 10. 64–75.9 MHz Input Frequency FM Receiver Characteristics (V = 2 1. Parameter Input Frequency Sensitivity with Headphone 3,4,5 Network 7 LNA Input Resistance 7 LNA Input Capacitance 8 Input IP3 3,4,7 AM Suppression Adjacent Channel Selectivity Alternate Channel Selectivity 3,4,7 Audio Output Voltage ...

Page 15

... Test Condition f Long Wave (LW) RF Medium Wave (AM) Short Wave (SW) (S+N)/ THD < 8% ΔV = 100 mV , 100 Hz DD RMS Long Wave (LW) Medium Wave (AM) From powerdown Rev. 1.0 Si4734/35-C40 Min Typ Max Unit 153 — 279 kHz 520 — 1710 kHz 2.3 — 26.1 MHz — ...

Page 16

... Crystal Frequency Tolerance Board Capacitance Notes: 1. The Si4734/35 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies between 31.130 kHz and 40 MHz that are not supported. For more details, see Table 6 of “AN332: Si47xx Programming Guide” frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing and AM seek/tune in SW frequencies ...

Page 17

... To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface. 6. Place Si4734/35 as close as possible to antenna and keep the FMI and AMI traces as short as possible ...

Page 18

... To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 6. Pin 8 connects to the FM antenna interface, and pin 12 connects to the AM antenna interface. 7. Place Si4734/35 as close as possible to antenna and keep the FMI and AMI traces as short as possible ...

Page 19

... C5 Coupling capacitor, 0.47 µF, ±20%, Z5U/X7R L1 Ferrite loop stick, 180 L2 4.7 µH U1 Si4734/35 AM/FM Radio Tuner C2, C3 Crystal load capacitors, 22 pF, ±5%, COG (Optional for crystal oscillator option) C4 Noise mitigating capacitor, 2~5 pF(Optional for digital audio) X1 32.768 kHz crystal (Optional for crystal oscillator option) R1 Resistor, 2 k ...

Page 20

... The Si4734/ feature-rich solution including advanced seek algorithms, soft mute, auto-calibrated digital tuning, and FM stereo processing. In addition, the Si4734/35 provides analog or digital audio output and a programmable reference clock. The device supports 20 RDS LNA ...

Page 21

... Operating Modes The Si4734/35 operates in either an FM receive or an AM/SW/LW receive mode mode, radio signals are received on FMI and processed by the FM front-end circuitry. In AM/SW/LW mode, radio signals are received on AMI and processed by the AM front-end circuitry. In addition to the receiver mode, there is a clocking mode to choose to clock the Si4734/35 from a reference clock or crystal ...

Page 22

... Si4734/35-C40 order, down to the LSB. The left channel is transferred first when the DFS is high, and the right channel is transferred when the DFS is low. In DSP mode, the DFS becomes a pulse with a width of 1DCLK period. The left channel is transferred first, followed right away by the right channel. There are two ...

Page 23

... Stereo/mono status can be monitored with the FM_RSQ_STATUS command. Mono operation FM_BLEND_MONO_THRESHOLD property. Rev. 1.0 Si4734/35-C40 RIGHT CHANNEL 1 DCLK n-2 n MSB ...

Page 24

... The serial port can operate in three bus modes: 2-wire mode, 3-wire mode, or SPI mode. The Si4734/35 selects the bus mode by sampling the state of the GPO1 and GPO2 pins on the rising edge of RST. The GPO1 pin includes an internal pull-up resistor, which is connected while Rev ...

Page 25

... SCLK. For read operations, the control word is followed by a delay of one-half SCLK cycle for bus turn-around. Next, the Si4734/35 will drive the 16-bit read data word serially on SDIO, changing the state of SDIO on each rising edge of SCLK. A transaction ends when the user sets SEN high, then pulses SCLK high and low one final time ...

Page 26

... Responses provide the user information and are echoed after a command and associated arguments are issued. All commands provide a 1-byte status update, indicating interrupt and clear-to-send status information. For a detailed description of the commands and properties for the Si4734/35, see “AN332: Si47xx Programming Guide.” Rev. 1.0 ...

Page 27

... Queries the status of the Received Signal Quality (RSQ) of the current channel. Returns RDS information for current channel and reads an entry from the RDS FIFO (Si4735 only). Selects the AM/SW/LW tuning frequency. Begins searching for a valid frequency. Queries the status of the RSQ of the current channel. Rev. 1.0 Si4734/35-C40 27 ...

Page 28

... Si4734/35-C40 Prop Name 0x1100 FM_DEEMPHASIS FM_BLEND_STEREO_ 0x1105 THRESHOLD FM_BLEND_MONO_ 0x1106 THRESHOLD FM_RSQ_INT_ 0x1200 SOURCE 0x1300 FM_SOFT_MUTE_RATE FM_SOFT_MUTE_ 0x1302 MAX_ATTENUATION FM_SOFT_MUTE_ 0x1303 SNR_THRESHOLD FM_SEEK_BAND_ 0x1400 BOTTOM 0x1401 FM_SEEK_BAND_TOP FM_SEEK_FREQ_ 0x1402 SPACING FM_SEEK_TUNE_ 0x1403 SNR_THRESHOLD FM_SEEK_TUNE_ 0x1404 RSSI_TRESHOLD 0x1500 RDS_INT_SOURCE 0x1501 RDS_INT_FIFO_COUNT 0x1502 ...

Page 29

... Sets the RSSI threshold for a valid AM/SW/LW Seek/Tune. If the value is zero, then RSSI threshold is not considered when doing a seek. Default value is 25 dBµV. Sets the output volume. Mutes the audio output. L and R audio outputs may be muted independently in FM mode. Rev. 1.0 Si4734/35-C40 Default 0x06AE 0x000A 0x0005 0x0019 0x003F ...

Page 30

... Si4734/35-C40 7. Pin Descriptions: Si4734/35-GM RFGND Pin Number(s) Name connect. Leave floating. 2 FMI FM RF inputs. FMI should be connected to the antenna trace. 3 RFGND RF ground. Connect to ground plane on PCB. 4 AMI AM/SW/LW RF input. 5 RST Device reset (active low) input. 6 SEN Serial enable input (active low). ...

Page 31

... Pin Descriptions: Si4734/35-GU Pin Number(s) Name 1 DOUT Digital output data in digital output mode. 2 DFS Digital frame synchronization input in digital output mode. 3 GPO3/DCLK General purpose output, crystal oscillator, or digital bit synchronous clock input in digital output mode. 4 GPO2/INT General purpose output or interrupt pin. ...

Page 32

... Si4734/35-C40 9. Ordering Guide Part Number* Si4734-C40-GM AM/FM/SW/LW Broadcast Radio Receiver Si4734-C40-GU AM/FM/SW/LW Broadcast Radio Receiver Si4735-C40-GM AM/FM/SW/LW Broadcast Radio Receiver with RDS/RBDS Si4735-C40-GU AM/FM/SW/LW Broadcast Radio Receiver with RDS/RBDS *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. SSOP devices operate down ° ...

Page 33

... Circle = 0.5 mm Diameter (Bottom-Left Justified Year WW = Workweek Si4734/35-C40 3540 CTTT YWW 34 = Si4734 Si4735 Firmware Revision 4. Revision C Die. Internal tracking code. Pin 1 Identifier. Assigned by the Assembly House. Corresponds to the last significant digit of the year and work week of the mold date. Rev. 1.0 ...

Page 34

... Top Mark Explanation (SSOP) Mark Method: YAG Laser Part Number Line 1 Marking: Die Revision Firmware Revision YY = Year Line 2 Marking Work week TTTTTT = Manufacturing code 34 4734C40GU YYWWTTTTTT 4734 = Si4734; 4735 = Si4735 Revision C die Firmware Revision 4.0. Assigned by the Assembly House. Rev. 1.0 ...

Page 35

... Package Outline: Si4734/35 QFN Figure 14 illustrates the package details for the Si4734/35. Table 16 lists the values for the dimensions shown in the illustration. Figure 14. 20-Pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A 0.50 0.55 A1 0.00 0.02 b 0.20 0.25 c 0.27 0.32 D 3.00 BSC D2 1 ...

Page 36

... Si4734/35-C40 12. PCB Land Pattern: Si4734/35 QFN Figure 15 illustrates the PCB land pattern details for the Si4734/35-C40-GM QFN. Table 17 lists the values for the dimensions shown in the illustration. 36 Figure 15. PCB Land Pattern Rev. 1.0 ...

Page 37

... A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. Notes: Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Si4734/35-C40 Symbol Millimeters Min GE 2.10 W — ...

Page 38

... Si4734/35-C40 13. Package Outline: Si4734/35 SSOP Figure 16 illustrates the package details for the Si4734/35. Table 18 lists the values for the dimensions shown in the illustration. Dimension θ aaa bbb ccc ddd Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. ...

Page 39

... PCB Land Pattern: Si4734/35 SSOP Figure 17 illustrates the PCB land pattern details for the Si4734/35-C40-GU SSOP. Table 19 lists the values for the dimensions shown in the illustration. Table 19. PCB Land Pattern Dimensions Dimension General: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...

Page 40

... Si4734/35-C40 15. Additional Reference Resources Contact your local sales representatives for more information or to obtain copies of the following references:  EN55020 Compliance Test Certificate  AN332: Si47xx Programming Guide  AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines  AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure 40 Rev ...

Page 41

... Updated Table 3 on page 5.  Updated Table 11 on page 15.  Updated "3. Typical Application Schematic (SSOP)" on page 18.  Updated "4. Bill of Materials (QFN/SSOP)" on page 19.  Updated "8. Pin Descriptions: Si4734/35-GU" on page 31.  Updated "9. Ordering Guide" on page 32. Si4734/35-C40 Rev. 1.0 41 ...

Page 42

... Si4734/35-C40 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: FMinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...

Related keywords