SI4735-C40-GU Silicon Laboratories Inc, SI4735-C40-GU Datasheet

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SI4735-C40-GU

Manufacturer Part Number
SI4735-C40-GU
Description
IC RX AM/FM/SW/LW RAD RDS 24SSOP
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI4735-C40-GU

Frequency
153kHz ~ 279kHz, 520kHz ~ 1.71MHz, 2.3MHz ~ 26.1MHz, 64MHz ~ 108MHz
Modulation Or Protocol
AM, FM, SW-LW
Applications
General Purpose
Current - Receiving
19.9mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Features
RSSI Equipped
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-20°C ~ 85°C
Package / Case
24-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Sensitivity
-
Memory Size
-
Data Rate - Maximum
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
B
Features
Applications
Description
The Si4734/35 is the first digital CMOS AM/FM radio receiver IC that integrates
the complete tuner function from antenna input to audio output.
Functional Block Diagram
Rev. 1.0 12/09
Worldwide FM band support
(64–108 MHz)
Worldwide AM band support
(520–1710 kHz)
SW band support
(2.3–26.1 MHz)
LW band support
(153–279 kHz)
Excellent real-world performance
Freq synthesizer with integrated VCO
Advanced seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Digital FM stereo decoder
Programmable AVC max gain
Programmable de-emphasis
Seven selectable AM channel filters
Table and portable radios
Stereos
Mini/micro systems
CD/DVD players
Boom boxes
ROADCAST
2.0–5.5 V (SSOP)
2.7–5.5 V (QFN)
AM / LW
ANT
FM / SW
ANT
RFGND
GND
VDD
AMI
FMI
LNA
LNA
AGC
AGC
LDO
AM/FM R
Copyright © 2009 by Silicon Laboratories
AFC
AM/FM/SW/LW digital tuning
EN55020 compliant
No manual alignment necessary
Programmable reference clock
Volume control
Adjustable soft mute control
RDS/RBDS processor (Si4735)
Optional digital audio out (Si4735)
2-wire and 3-wire control interface
Integrated LDO regulator
2.0 to 5.5 V supply voltage (SSOP)
2.7 to 5.5 V supply voltage (QFN)
Wide range of ferrite loop sticks and
air loop antennas supported
QFN and SSOP packages
ADC
ADC
Modules
Clock radios
Mini HiFi
Entertainment systems
RoHS compliant
(Si4735)
LOW-IF
ADIO
RDS
DSP
INTERFACE
Si4734/35
CONTROL
DIGITAL
(Si4735)
AUDIO
DAC
DAC
R
GPO/DCLK
ECEIVER
DOUT
ROUT
LOUT
VIO
1.85-3.6 V
DFS
S i 4 7 3 4 / 3 5 - C 4 0
This product, its features, and/or its
architecture is covered by one or more of
the following patents, as well as other
patents, pending and issued, both foreign
and
7,272,375;
7,426,376;
7,339,504.
RFGND
GPO3/DCLK
GPO2/INT
domestic:
RST
AMI
FMI
NC
RFGND
Ordering Information:
DOUT
GPO1
DFS
FMI
AMI
Si4734/35 (SSOP)
NC
NC
NC
NC
Pin Assignments
2
3
4
5
Si4734/35 (QFN)
1
6
See page 32.
20
7
7,321,324;
7,471,940;
10
11
12
1
2
3
4
5
6
7
8
9
7,127,217;
19
8
GND
PAD
18
9
17
10
Si4734/35-C40
24
23
22
21
20
19
18
17
16
15
14
13
16
11
15 DOUT
14
13
12
7,272,373;
7,355,476;
7,339,503;
ROUT
DBYP
VDD
LOUT
VIO
RCLK
SDIO
SCLK
SEN
RST
GND
GND
LOUT
ROUT
GND
VDD

Related parts for SI4735-C40-GU

SI4735-C40-GU Summary of contents

Page 1

... Programmable reference clock  Volume control  Adjustable soft mute control  RDS/RBDS processor (Si4735)  Optional digital audio out (Si4735)  2-wire and 3-wire control interface  Integrated LDO regulator  2.0 to 5.5 V supply voltage (SSOP)  2.7 to 5.5 V supply voltage (QFN)  ...

Page 2

Si4734/35-C40 2 Rev. 1.0 ...

Page 3

... LW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.7. Digital Audio Interface (Si4735 Only 5.8. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.9. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.10. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.11. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.12. RDS/RBDS Processor (Si4735 Only .24 5.13. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.14. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.15. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.16. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.17. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.18. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 5 ...

Page 4

Si4734/35-C40 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter 2 Supply Voltage Interface Supply Voltage Power Supply Powerup Rise Time Interface Power Supply Powerup Rise Time Ambient Temperature Note: 1. All minimum and maximum specifications apply across the recommended ...

Page 5

Table 3. DC Characteristics (V = 2 1. Parameter FM Mode 1 Supply Current 2 Supply Current 1 RDS Supply Current AM/SW/LW Mode 1 Supply Current Supplies and Interface ...

Page 6

Si4734/35-C40 Table 4. Reset Timing Characteristics (V = 2 1. Parameter RST Pulse Width and GPO1, GPO2/INT Setup to RST GPO1, GPO2/INT Hold from RST Important Notes: 1. When ...

Page 7

Table 5. 2-Wire Control Interface Characteristics (V = 2 1. Parameter SCLK Frequency SCLK Low Time SCLK High Time  SCLK Input to SDIO Setup (START)  SCLK Input ...

Page 8

Si4734/35-C40 SU:STA HD:STA LOW 70% SCLK 30% 70% SDIO 30% START t r:IN Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, SDIO R/W START ADDRESS + R/W Figure 3. 2-Wire Control Interface Read ...

Page 9

Table 6. 3-Wire Control Interface Characteristics (V = 2 1. Parameter SCLK Frequency SCLK High Time SCLK Low Time SDIO Input, SEN to SCLKSetup SDIO Input to SCLKHold  ...

Page 10

Si4734/35-C40 Table 7. SPI Control Interface Characteristics (V = 2 1. Parameter SCLK Frequency SCLK High Time SCLK Low Time SDIO Input, SEN to SCLKSetup SDIO Input to SCLKHold ...

Page 11

Table 8. Digital Audio Interface Characteristics (V = 2 1. Parameter DCLK Cycle Time DCLK Pulse Width High DCLK Pulse Width Low DFS Set-up Time to DCLK Rising Edge ...

Page 12

Si4734/35-C40 Table 9. FM Receiver Characteristics (V = 2 1. Parameter Input Frequency Sensitivity with Headphone 3,4,5 Network Sensitivity with 50  Network 3,4,5,6 6 RDS Sensitivity 6,7 LNA ...

Page 13

Table 9. FM Receiver Characteristics (V = 2 1. Parameter 3,4,5,6,12,13 Blocking Sensitivity 3,4,5,6,12,13 Intermode Sensitivity 6,10 Audio Output Load Resistance 6,10 Audio Output Load Capacitance 6 Seek/Tune Time ...

Page 14

Si4734/35-C40 Table 10. 64–75.9 MHz Input Frequency FM Receiver Characteristics (V = 2 1. Parameter Input Frequency Sensitivity with Headphone 3,4,5 Network 7 LNA Input Resistance 7 LNA Input ...

Page 15

Table 11. AM/SW/LW Receiver Characteristics (V = 2 1. – ° Parameter Symbol Input Frequency 3,4,5,6 Sensitivity Large Signal Voltage 4,6,7 Handling 6 Power Supply Rejection ...

Page 16

Si4734/35-C40 Table 12. Reference Clock and Crystal Characteristics (V = 2 1. Parameter 1 RCLK Supported Frequencies 2 RCLK Frequency Tolerance REFCLK_PRESCALE REFCLK Crystal Oscillator Frequency 2 Crystal Frequency ...

Page 17

Typical Application Schematic (QFN FMI FMI C4 3 RFGND AMI C5 5 RST RST SEN SCLK SDIO RCLK VIO 1.85 to 3.6 V Notes: 1. Place C1 close to V pin ...

Page 18

Si4734/35-C40 3. Typical Application Schematic (SSOP) Optional: Digital Audio Output DOUT C4 DFS GPO3/DCLK GPO2/INT GPO1 NC NC FMI C4 RFGND GPIO3 C2 Optional: for crystal oscillator option Notes: 1. Place C1 close to ...

Page 19

Bill of Materials (QFN/SSOP) Component(s) C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R C5 Coupling capacitor, 0.47 µF, ±20%, Z5U/X7R L1 Ferrite loop stick, 180 L2 4.7 µH U1 Si4734/35 AM/FM Radio Tuner C2, C3 Crystal load capacitors, 22 ...

Page 20

... The Si4735 incorporates a digital processor for the European Radio Data System (RDS) and the North American Radio Broadcast Data System (RBDS), including all synchronization, error detection, and error correction functions ...

Page 21

... AMI and processed by the AM front-end circuitry. In addition to the receiver mode, there is a clocking mode to choose to clock the Si4734/35 from a reference clock or crystal. On the Si4735, there is an audio output mode to choose between an analog and/or digital audio output. In the analog audio output mode, ROUT and LOUT are used for the audio output pins ...

Page 22

Si4734/35-C40 order, down to the LSB. The left channel is transferred first when the DFS is high, and the right channel is transferred when the DFS is low. In DSP mode, the DFS becomes a pulse with a width of ...

Page 23

... Output left and right channels are obtained by adding and subtracting the (L+R) and (L–R) signals respectively. The Si4735 uses frequency information from the 19 kHz stereo pilot to recover the 57 kHz RDS/RBDS signal. 5.8.2. Stereo-Mono Blending ...

Page 24

... The Si4735 device is user configurable and provides an optional interrupt when RDS is synchronized, loses synchronization, and/or the user configurable RDS FIFO threshold has been met. The Si4735 reports RDS decoder synchronization status and detailed bit errors in the information word for each RDS block with the FM_RDS_STATUS command. The range of reportable block errors is 0, 1– ...

Page 25

RST is low, and the GPO2 pin includes an internal pull- down resistor, which is connected while RST is low. Therefore only necessary for the user to actively drive pins which differ from these states. See Table 13. ...

Page 26

Si4734/35-C40 5.16.3. SPI Control Interface Mode When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. SPI bus mode uses the SCLK, SDIO, and ...

Page 27

... Queries the status of the Received Signal Quality (RSQ) of the current channel. Returns RDS information for current channel and reads an entry from the RDS FIFO (Si4735 only). Selects the AM/SW/LW tuning frequency. Begins searching for a valid frequency. Queries the status of the RSQ of the current channel. ...

Page 28

Si4734/35-C40 Prop Name 0x1100 FM_DEEMPHASIS FM_BLEND_STEREO_ 0x1105 THRESHOLD FM_BLEND_MONO_ 0x1106 THRESHOLD FM_RSQ_INT_ 0x1200 SOURCE 0x1300 FM_SOFT_MUTE_RATE FM_SOFT_MUTE_ 0x1302 MAX_ATTENUATION FM_SOFT_MUTE_ 0x1303 SNR_THRESHOLD FM_SEEK_BAND_ 0x1400 BOTTOM 0x1401 FM_SEEK_BAND_TOP FM_SEEK_FREQ_ 0x1402 SPACING FM_SEEK_TUNE_ 0x1403 SNR_THRESHOLD FM_SEEK_TUNE_ 0x1404 RSSI_TRESHOLD 0x1500 RDS_INT_SOURCE 0x1501 RDS_INT_FIFO_COUNT ...

Page 29

Table 15. Selected Si473x Properties (Continued) Prop Name 0x3401 AM_SEEK_BAND_TOP AM_SEEK_FREQ_ 0x3402 SPACING AM_SEEK_SNR_ 0x3403 THRESHOLD AM_SEEK_RSSI_ 0x3404 THRESHOLD 0x4000 RX_VOLUME 0x4001 RX_HARD_MUTE Description Sets the top of the AM/SW/LW band for seek. Selects frequency spacing for AM/SW/LW seek. Default ...

Page 30

Si4734/35-C40 7. Pin Descriptions: Si4734/35-GM RFGND Pin Number(s) Name connect. Leave floating. 2 FMI FM RF inputs. FMI should be connected to the antenna trace. 3 RFGND RF ground. Connect to ground plane on PCB. 4 ...

Page 31

Pin Descriptions: Si4734/35-GU Pin Number(s) Name 1 DOUT Digital output data in digital output mode. 2 DFS Digital frame synchronization input in digital output mode. 3 GPO3/DCLK General purpose output, crystal oscillator, or digital bit synchronous clock input in ...

Page 32

... AM/FM/SW/LW Broadcast Radio Receiver Si4735-C40-GM AM/FM/SW/LW Broadcast Radio Receiver with RDS/RBDS Si4735-C40-GU AM/FM/SW/LW Broadcast Radio Receiver with RDS/RBDS *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. SSOP devices operate down ° ...

Page 33

... Circle = 0.5 mm Diameter (Bottom-Left Justified Year WW = Workweek Si4734/35-C40 3540 CTTT YWW 34 = Si4734 Si4735 Firmware Revision 4. Revision C Die. Internal tracking code. Pin 1 Identifier. Assigned by the Assembly House. Corresponds to the last significant digit of the year and work week of the mold date. Rev. 1.0 ...

Page 34

... Top Mark Explanation (SSOP) Mark Method: YAG Laser Part Number Line 1 Marking: Die Revision Firmware Revision YY = Year Line 2 Marking Work week TTTTTT = Manufacturing code 34 4734C40GU YYWWTTTTTT 4734 = Si4734; 4735 = Si4735 Revision C die Firmware Revision 4.0. Assigned by the Assembly House. Rev. 1.0 ...

Page 35

Package Outline: Si4734/35 QFN Figure 14 illustrates the package details for the Si4734/35. Table 16 lists the values for the dimensions shown in the illustration. Figure 14. 20-Pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A 0.50 0.55 ...

Page 36

Si4734/35-C40 12. PCB Land Pattern: Si4734/35 QFN Figure 15 illustrates the PCB land pattern details for the Si4734/35-C40-GM QFN. Table 17 lists the values for the dimensions shown in the illustration. 36 Figure 15. PCB Land Pattern Rev. 1.0 ...

Page 37

Table 17. PCB Land Pattern Dimensions Symbol Millimeters Min Max D 2.71 REF D2 1.60 1.80 e 0.50 BSC E 2.71 REF E2 1.60 1.80 f 2.53 BSC GD 2.10 — Notes: General 1. All dimensions shown are in millimeters ...

Page 38

Si4734/35-C40 13. Package Outline: Si4734/35 SSOP Figure 16 illustrates the package details for the Si4734/35. Table 18 lists the values for the dimensions shown in the illustration. Dimension θ aaa ...

Page 39

PCB Land Pattern: Si4734/35 SSOP Figure 17 illustrates the PCB land pattern details for the Si4734/35-C40-GU SSOP. Table 19 lists the values for the dimensions shown in the illustration. Table 19. PCB Land Pattern Dimensions Dimension ...

Page 40

Si4734/35-C40 15. Additional Reference Resources Contact your local sales representatives for more information or to obtain copies of the following references:  EN55020 Compliance Test Certificate  AN332: Si47xx Programming Guide  AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines ...

Page 41

OCUMENT HANGE IST Revision 0.71 to Revision 1.0  Updated patent information on page 1.  Pin 22 changed from “GND” to “DBYP.”  Updated Table 1 on page 4.  Updated Table 3 on page 5. ...

Page 42

... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...

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