TDA5230 Infineon Technologies, TDA5230 Datasheet - Page 110

• Manufacturer Part Number: TDA5230
• Description: IC RECEIVER ASK/FSK 28-TSSOP
• Manufacturer: Infineon Technologies
• Type: Receiverr

Specifications of TDA5230

• Package / Case: 28-TSSOP
• Frequency: 433MHz ~ 450MHz, 865MHz ~ 868MHz
• Sensitivity: -111dBm
• Data Rate - Maximum: 20 kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Operating Frequency: 870 MHz
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: SP000076520; TDA5230; TDA5230INTR

TDA523x
Functional Description
clock recovery reset
start point
valid data
valid data
TSI A
TSI GAP
TSI B
RUNIN
GAPSync
< 1bit
< 1bit
PLL sync
internal PLL sync
Figure 54
Clock Recovery GAP Re-synchronization Mode 1
When the time TSI GAP in the start sequence of the transmitted telegram has elapsed,
the receiver needs a certain time (GAPSync = 5...6 chips) to readjust the PLL settings.
Behavior of the system at the starting position of the TSI B:
The starting position (TSI B start) for the TSI B comparison is independent from the
RUNIN settings (CDR2 register) and the Re-synchronization mode (TSIMODE register):
[
]
[
]
TSIBstart chips
=
TSIGAP chips
+
6…8
The incoming chips at TSI B start and the following incoming chips are compared with
the contents of the register TSI B. Please notice that the receiver’s PLL runs at the data
rate determined before the gap. Therefore, the receiver calculates the gap based on this
data rate.
Behavior of the system at the ending position of TSI B:
The system checks for the TSI B to match within a limited time. If there is no match within
this time, then the receiver starts again to search for the TSI A pattern at the following
incoming chips:
[
]
[
]
[
]
TSIBstop chips
=
TSIGAP chips
+
TSILENB chips
+
11
For a successful TSI B pattern match, the defined TSI B pattern must be between “Start
of TSIB” and “Stop of TSI B”. In the example below, the earliest possible start position
th
nd
would be the 18
chip and the latest possible start position would be the 22
chip.
Please note that after a gap the internal TSI comparison register is cleared (all chips set
to ’0’). In this case, a TSI B criteria of “0000” would always match at the beginning. To
avoid such an unwanted matching, set the highest TSI B match chip to ’1’.
Data Sheet
106
Version 4.0, 2007-06-01