TDA5230 Infineon Technologies, TDA5230 Datasheet - Page 119

• Manufacturer Part Number: TDA5230
• Description: IC RECEIVER ASK/FSK 28-TSSOP
• Manufacturer: Infineon Technologies
• Type: Receiverr

Specifications of TDA5230

• Package / Case: 28-TSSOP
• Frequency: 433MHz ~ 450MHz, 865MHz ~ 868MHz
• Sensitivity: -111dBm
• Data Rate - Maximum: 20 kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Operating Frequency: 870 MHz
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: SP000076520; TDA5230; TDA5230INTR

2.4.15
The Data FIFO is the storage for the received data frames. It is written during data
reception. The host microcontroller is able to start reading via SPI right after frame sync
(interrupt). The FIFO can store up to 128 received data bits. If the expected data
transmission contains more bits (note that in TSI 8-Bit Mode Extended the first bit is used
to indicate which of the two TSI pattern has matched), reading must start after frame
sync to prevent an overrun.
Architecture:
The 128-bit data FIFO is based on a bit addressable 2-port memory architecture.
Figure 60
The write port is controlled by the Digital Receiver using the Write Address Pointer.
Writing data into the FIFO starts with the detection of a TSI. The Write Address Pointer
is incremented with each data clock signal generated by the Digital Receiver. The read
port is controlled by the SPI controller using the Read Address Pointer. Each bit read
from the SPI controller increments the Read Address Pointer. The Read and Write
Data Sheet
Receiver
Receiver
Digital-
Digital-
from FSM
from
from
FSINITFIFO
INITFIFO
Data
Data Clock
InitFIFO
FSync
EOM
FIFOLK
Data FIFO
Data FIFO
Write Address
ENABLE
(Up-Counter)
Controller
Pointer
FIFO-
RESET
FIFO-Overflow
# of Valid Bits
Bit-Address
Write-Port
115
1 of 8 Decoder
Memory-Array
SDO-Frame
8 to 1 MUX
Generator
128-bit
byte 10
byte 11
byte 12
byte 13
byte 14
byte 15
Out
byte 0
byte 1
byte 2
byte 3
byte 4
byte 5
byte 6
byte 7
byte 8
byte 9
In
Read-Port
Bit-Address
RESET
Read Address
(Up-Counter)
Pointer
Functional Description
ENABLE
Version 4.0, 2007-06-01
SCLK
TDA523x
fifolk
SDO
to
SPI-Bus
to FSM