TDA5230 Infineon Technologies, TDA5230 Datasheet - Page 39

• Manufacturer Part Number: TDA5230
• Description: IC RECEIVER ASK/FSK 28-TSSOP
• Manufacturer: Infineon Technologies
• Type: Receiverr

Specifications of TDA5230

• Package / Case: 28-TSSOP
• Frequency: 433MHz ~ 450MHz, 865MHz ~ 868MHz
• Sensitivity: -111dBm
• Data Rate - Maximum: 20 kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Operating Frequency: 870 MHz
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: SP000076520; TDA5230; TDA5230INTR

2.4.5.2
In Run Mode Slave, the receiver is able to continuously scan for incoming data streams.
Detection and validation of a wake up pattern are not done, but correct RUNIN and TSI
are required.
Recognition of TSI and validation of the optional MID (Message IDentification) are done
automatically. The data payload is extracted from the data stream, and moved to the
FIFO.
The various recognition steps are communicated by interrupts. Interrupts are generated
at Framestart (when a valid TSI has been detected), when a valid MID has been found,
and at EOM (End of Message).
Run Mode Slave is entered by setting SFR CMC0 bits MSEL to 0 and SLRXEN to 1.
Configurations are switched via SFR bit RMSL in the CMC0 register. The channel in use
is always defined in the ARFPPLL and BRFPLL SFRs, depending on the selected
configuration.
The configuration may be changed only in Sleep Mode or in Hold Mode. This is
necessary to restart the state machine with defined settings at a defined state. Otherwise
the state machine may hang up. Re-configurations using Hold Mode is faster, because
there is no Start Up sequence.
CMC0:
ADDR:
Figure 18
Mode Slave.
Data Sheet
Bit R/W Description
3
W
0x02
Chip Mode Control Register 0
Run Mode Slave
illustrates the internal behavior of the FSM (Finite State Machine) in Run
RMSL: Run Mode Slave Configuration
This Bit is relevant only in Slave Mode, to select the used configuration
0: Config A
1: Config B
35
Functional Description
Reset Value: 0x40
Version 4.0, 2007-06-01
TDA523x