MRF49XA-I/ST Microchip Technology, MRF49XA-I/ST Datasheet
MRF49XA-I/ST
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MRF49XA-I/ST Summary of contents
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... Microchip Technology Inc. MRF49XA Data Sheet ISM Band Sub-GHz RF Transceiver Preliminary DS70590B ...
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... PICDEM, PICDEM.net, PICtail, PIC Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Integrated Low Phase Noise VCO Frequency • Synthesizer and PLL Loop Filter • Automatic Frequency Control © 2009 Microchip Technology Inc. MRF49XA Baseband Features • Supports Programmable TX Frequency Deviation and RX Baseband Bandwidth • Analog and Digital RSSI Outputs with Dynamic Range • ...
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... MRF49XA Pin Diagram: 16-Pin TSSOP FSK/DATA/FSEL RCLKOUT/FCAP/FINT CLKOUT DS70590B-page 2 SDI 1 16 SCK SDO 13 4 MRF49XA IRQ Preliminary INT/DIO RSSIO V DD RFN RFP V SS RESET RFXTL/EXTREF © 2009 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. Preliminary MRF49XA DS70590B-page 3 ...
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... MRF49XA NOTES: DS70590B-page 4 Preliminary © 2009 Microchip Technology Inc. ...
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... MHz frequency bands, and for applications looking for FCC ETSI certification in the ISM band. The MRF49XA has a low phase noise and provides an excellent adjacent channel interference, Bit Error Rate (BER) and larger communication coverage along with higher output power. The MRF49XA device’ ...
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... MRF49XA FIGURE 1-1: FUNCTIONAL NODE BLOCK DIAGRAM Antenna Matching Circuitry FIGURE 1-2: MICROCONTROLLER TO MRF49XA INTERFACE ® PIC * Implies optional signals. DS70590B-page 6 MRF49XA RF Block RFP PA/LNA Baseband Data RFN and Amplifier/ Processing PLL/CLK Filter/Limiter Unit Block Power Memory Management 10 MHz MCU MRF49XA ...
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... HARDWARE DESCRIPTION The MRF49XA is an integrated, single chip ISM Band Sub-GHz Transceiver. A simplified architectural block diagram of the MRF49XA is shown in Figure 2-1. The frequency synthesizer is clocked by an external 10 MHz crystal and generates the 433, 868 and 915 MHz radio frequency. The receiver with a Zero-IF architecture consists of the following components: • ...
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... FIGURE 2-1: MRF49XA ARCHITECTURAL BLOCK DIAGRAM MIX I LNA RFN 13 RFP 12 MIX Q PA PLL and I/Q VCO with Calibration PA/LNA and PLL/CLK Block WUTM CLK OSC with calibration Clock Block 8 9 RFXTL/ CLKOUT EXTREF Cal AMP Ckt I/Q DEMOD Self Calibration Cal ...
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... CLKOUT Digital Output © 2009 Microchip Technology Inc. Type Serial data input interface to MRF49XA (SPI input signal). Serial clock interface (SPI clock). Serial interface chip select (SPI chip/device select). Serial data output interface from MRF49XA (SPI output signal). Interrupt Request Output: Receiver generates an ...
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... MRF49XA TABLE 2-1: PIN DESCRIPTION (CONTINUED) Pin Symbol 9 RFXTL/EXTREF Analog Input 10 RESET Digital Input/Output Active-low hardware pin. This pin has an open-drain Reset 11 Vss 12 RFP RF Input/Output 13 RFN RF Input/Output RSSIO Analog Input/Output Received Signal Strength Indicator Output: The analog 16 INT/DIO Digital Input/Output Interrupt: This pin can be configured as an active-low ...
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... Tantalum Ceramic 2.2 RESET Pin An external hardware Reset of MRF49XA can be per- formed by asserting the RESET (pin 10) to low. After releasing the pin, it takes slightly more than 0.25 ms for the transceiver to be released from the Reset. The pin is driven with an open-drain output, and hence pulled down while the device is in POR ...
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... DS70590B-page 12 2.7 Automatic Frequency Control The PLL in MRF49XA is capable of performing auto- matic fine adjustment for the carrier frequency by using an integrated Automatic Frequency Control (AFC) feature. The receiver uses the AFC feature to minimize the frequency offset between the TX/RX signals in discrete steps, which gives the advantage of: • ...
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... Data Validity Blocks 2.10.1 RECEIVE SIGNAL STRENGTH INDICATOR The MRF49XA provides the RSSI signal to the host microcontroller, and hence, supports the monitoring of analog and digital signal strengths. A digital RSSI output is provided to monitor the input signal level through an internal STATUS register. The digital RSSI goes high, if the received signal strength exceeds a given prepro- grammed RSSI threshold level ...
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... Sleep. 2.11.3 LOW DUTY CYCLE MODE The MRF49XA can be made to enter into a Low Duty Cycle mode operation to decrease the average power consumption in Receive mode. The Low Duty Cycle mode is normally used in conjunction with the wake-up timer for its operation ...
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... The SDO pin defaults to a low state when the CS pin is high (the MRF49XA is not selected). This pin has a tri-state buffer and uses a bus hold logic. For the SPI interface, see Figure 4-1. The following parameters can be programmed and set through SPI: • ...
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... MRF49XA 2.16 Memory Organization The memory in MRF49XA is implemented as static RAM and is accessible via the SPI port. Each memory location functionally addresses a register, control, status or data/FIFO fields, as shown in Table 2-5. The command/control registers provide control, status and device address for transceiver operations. The FIFOs serve as temporary buffers for data transmission and reception ...
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TABLE 2-5: CONTROL (COMMAND) REGISTER MAP Reg. Name Bit 15 Bit 14 Bit 13 Bit 12 STSREG TXRXFIFO POR TXOWRXOF WUTINT LCEXINT GENCREG AFCCREG TXCREG TXBREG 1 0 ...
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... MRF49XA 2.17 Control Command Register Details ( ) REGISTER 2-1: STSREG: STATUS READ REGISTER (POR: 0x0000) R-0 R-0 R-0 TXRXFIFO POR TXOWRXOF bit 15 R-0 R-0 R-0 DQDO CLKRL AFCCT bit reserved bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ...
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... The actual frequency offset can be calculated as the AFC offset value multiplied by the current PLL frequency step from CFSREG (FREQB<11:0>). This bit is cleared after STSREG is read. 5: See Appendix A: “Read Sequence and Packet Structures” for the STSREG read sequence,. Note: © 2009 Microchip Technology Inc. (1) (CONTINUED) Preliminary MRF49XA (4) DS70590B-page 19 ...
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... MRF49XA REGISTER 2-2: GENCREG: GENERAL CONFIGURATION REGISTER (POR: 0x8008) R/W-1 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 TXDEN FIFOEN bit reserved bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 CCB<15:8>: Command Code bits The command code bits (10000000b) are serially sent to the microcontroller to identify the bits to be written in the GENCREG ...
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... Microchip Technology Inc. R/W-0 R/W-0 CCB<15:8> R/W-1 R/W-0 ARFO<1:0> MFCS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) RES (3) Preliminary MRF49XA R/W-1 R/W-0 R/W-0 bit 8 R/W-1 R/W-1 R/W-1 HAM FOREN FOFEN bit Bit is unknown (2) for each band is as follows: ...
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... MRF49XA REGISTER 2-3: AFCCREG: AUTOMATIC FREQUENCY CONTROL CONFIGURATION REGISTER (POR: 0xC4F7) (CONTINUED) bit 0 FOFEN: Frequency Offset Enable bit 1 = Enables the frequency offset calculation using the AFC circuit 0 = Disables the frequency offset calculation using the AFC circuit The F is the frequency tuning resolution for each band. The F ...
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... The output transmit power range is relative to the maximum available power, which depends on the actual 2: antenna impedance. © 2009 Microchip Technology Inc. R/W-1 R/W-1 R/W-0 CCB<15:9> R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF49XA R/W-0 R/W-0 MODPLY bit 8 R/W-0 R/W-0 OTXPWR<2:0> bit Bit is unknown (1) DS70590B-page 23 ...
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... MRF49XA REGISTER 2-4: TXCREG: TRANSMIT CONFIGURATION REGISTER (POR: 0x9800) (CONTINUED) bit 2-0 OTXPWR<2:0>: Output Transmit Power Range bits These bits set the transmit output power range. The output power is programmable from 0 dB (Max.) to -17 -2.5 dB steps. 111 = -17.5 dB 110 = -15.0 dB 101 = -12.5 dB 100 = -10 ...
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... TXDEN = 1 (GENCREG<7>). If TXDEN is not set, use the FSK/DATA/FSEL pin to manually modulate the data. © 2009 Microchip Technology Inc. R/W-1 R/W-1 R/W-0 CCB<15:8> R/W-0 R/W-1 R/W-0 TXDB<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF49XA R/W-0 R/W-0 bit 8 R/W-1 R/W-0 bit Bit is unknown DS70590B-page 25 ...
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... MRF49XA REGISTER 2-6: CFSREG: CENTER FREQUENCY VALUE SET REGISTER (POR: 0xA680) R/W-1 R/W-0 R/W-1 CCB<15:12> bit 15 R/W-1 R/W-0 R/W-0 bit reserved bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 CCB<15:12>: Command Code bits The command code bits (1010b) are serially sent to the microcontroller to identify the bits to be written in the CFSREG ...
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... LNA gain also affects the true RSSI value - - © 2009 Microchip Technology Inc. R/W-1 R/W-0 R/W-0 FINTDIO R/W-0 R/W-0 R/W-0 RXLNA<1:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF49XA R/W-0 R/W-0 DIORT<1:0> bit 8 R/W-0 R/W-0 DRSSIT<2:0> bit Bit is unknown DS70590B-page 27 ...
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... MRF49XA REGISTER 2-7: RXCREG: RECEIVE CONTROL REGISTER (POR: 0x9080) (CONTINUED) bit 2-0 DRSSIT<2:0>: Digital RSSI Threshold bits These bits can be set to indicate the incoming signal strength above a preset limit. The result enables or disables the DQDO bit (STSREG<7>). 111 = Reserved 110 = Reserved ...
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... Microchip Technology Inc. R/W-0 R/W-0 R/W-0 CCB<15:8> R/W-0 R/W-1 R/W-1 FTYPE Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) . Table 2-7 shows the optimum filter capacitor values for different SS Preliminary MRF49XA R/W-1 R/W-0 bit 8 R/W-0 R/W-0 DQTI<2:0> bit Bit is unknown DS70590B-page 29 ...
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... MRF49XA EQUATION 2-3: DQI = 4 x (Deviation – TX/RX )/Bit Rate par offset DS70590B-page 30 TABLE 2-8: DATA RATE CAPACITOR VALUE Data Rate 1.2 kbps 2.4 kbps 4.8 kbps 9.6 kbps 19.2 kbps 38.4 kbps 57.6 kbps 115.2 kbps 256 kbps Preliminary © 2009 Microchip Technology Inc. ...
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... FIFO over the SPI bus. The FIFOEN bit (GENCREG<6>) should be set to receive these bits. © 2009 Microchip Technology Inc. R/W-1 R/W-0 R/W-0 CCB<15:8> R/W-0 R/W-0 R/W-0 RXDB<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF49XA R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown DS70590B-page 31 ...
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... MRF49XA REGISTER 2-10: FIFORSTREG: FIFO AND RESET MODE CONFIGURATION REGISTER (POR: 0xCA80) R/W-1 R/W-1 R/W-0 bit 15 R/W-1 R/W-0 R/W-0 FFBC<3:0> bit reserved bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 CCB<15:8>: Command Code bits The command code bits (11001010b) are serially sent to the microcontroller to identify the bits to be written in the FIFORSTREG ...
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... See Appendix A: “Read Sequence and Packet Structures” for FIFO packet structures. Note: © 2009 Microchip Technology Inc. SCL1 SCL0 NA 0xD4 0x2D 0xD4 Reset is triggered when V Reset is triggered when V is greater than 600 mV Preliminary MRF49XA Synchronous Character 0xD4 (byte long) 0x2DD4 (word long) Condition is below 250 below 1.6V and V glitch DD DD DS70590B-page 33 ...
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... MRF49XA REGISTER 2-11: SYNBREG: SYNCHRONOUS BYTE CONFIGURATION REGISTER (POR: 0xCED4) R/W-1 R/W-1 R/W-0 bit 15 R/W-1 R/W-1 R/W-0 bit reserved bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 CCB<15:8>: Command Code bits The command code bits (11001110b) are serially sent to the microcontroller to identify the bits to be written in the SYNBREG ...
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... DR is the expected data rate set using DRPV<6:0>. © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-1 CCB<15:8> R/W-0 R/W-0 R/W-0 (1) DRPV<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary MRF49XA R/W-1 R/W-0 bit 8 R/W-1 R/W-1 bit Bit is unknown DS70590B-page 35 ...
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... MRF49XA REGISTER 2-13: PMCREG: POWER MANAGEMENT CONFIGURATION REGISTER (POR: 0x8208) R/W-1 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 (1) RXCEN BBCEN TXCEN bit reserved bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 CCB<15:8>: Command Code bits The command code bits (10000010b) are serially sent to the microcontroller to identify the bits to be written in the PMCREG ...
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... See WTSREG (Register 2-14) for details on programming the wake-up timer value the CLKOEN bit is cleared by enabling the clock output, the oscillator continues to run even if the 4: OSCEN bit is cleared. The device will not fully enter into the Sleep mode. © 2009 Microchip Technology Inc. (2) (4) Preliminary MRF49XA DS70590B-page 37 ...
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... MRF49XA REGISTER 2-14: WTSREG: WAKE-UP TIMER VALUE SET REGISTER (POR: 0xE196) R/W-1 R/W-1 R/W-1 CCB<15:13> bit 15 R/W-1 R/W-0 R/W-0 bit reserved bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 CCB<15:13>: Command Code bits The command code bits (111b) are serially sent to the microcontroller to identify the bits to be written in the WTSREG ...
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... The DCSREG can be set up so that when the wake-up timer brings the MRF49XA out of Sleep mode, the receiver is turned on for a short period to sample the signal presence before returning to Sleep. The process in the Duty Cycle mode starts over. The duty cycle uses the multiplier value of the wake-up timer, in parts for its calculation, as shown in Equation 2-8 ...
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... MRF49XA REGISTER 2-16: BCSREG: BATTERY THRESHOLD DETECT AND CLOCK OUTPUT VALUE SET REGISTER (POR: 0xC000) R/W-1 R/W-1 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 COFSB<2:0> bit reserved bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 CCB<15:8>: Command Code bits The command code bits (11000000b) are serially sent to the microcontroller to identify the bits to be written in the BCSREG ...
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... Microchip Technology Inc. R/W-0 R/W-1 R/W-1 CCB<15:8> R/W-1 R/W-0 R/W-1 r PDDS PLLDD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary MRF49XA R/W-0 R/W-0 bit 8 R/W-1 R/W-1 r PLLBWB bit Bit is unknown DS70590B-page 41 ...
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... MRF49XA NOTES: DS70590B-page 42 Preliminary © 2009 Microchip Technology Inc. ...
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... FSK transceiver which operates in the 433, 868 and 915 MHz frequency bands. All the RF and baseband functions and processes are integrated in the MRF49XA. The device for its operation requires only a single, 10 MHz crystal as a reference source and an external, low-cost host microcontroller. The MRF49XA supports the following functions: • ...
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... MRF49XA 3.1.2 POWER GLITCH RESET Spikes or glitches are found on the V DD supply filtering is not satisfactory, or the internal resis- tance of the power supply is very high. So, in this case, the Sensitive Reset mode needs to be enabled. Here, the device Reset occurs due to the transients present on the V line ...
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... POR, but the duration of the Reset event is much less than the actual POR (0.25 ms, typical). 3.1.4 RESET PIN The MRF49XA has an open-drain Reset output with an internal pull-up and input buffer (active-low). The host microcontroller resets the MRF49XA by asserting the RESET pin to low (see Figure 3-4). All control registers are reset to their POR values ...
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... A small amount of parasitic capacitance is needed to facilitate oscillation. To achieve this, create a ground plane around the crystal and widen the connection to the MRF49XA. This is to adjust the ref- erence frequency and to compensate for stray capaci- tance that might be introduced due to PCB layout. If the layout is not possible ...
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... PLL to incrementally change the carrier frequency. The MRF49XA can be programmed to automatically change and control the carrier frequency. The carrier frequency can also be manually activated by a strobe signal ...
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... MRF49XA 3.6 Crystal Selection Guidelines The crystal oscillator of MRF49XA requires a 10 MHz Parallel mode crystal. The circuit contains an inte- grated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can pF variety of crystal types can be used ...
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... AFC has to be disabled during read by clearing the FOFEN bit (AFCCREG<0>). The registers associated with AFC are: • STSREG (see Register 2-1) • AFCCREG (see Register 2-3) • CFSREG (see Register 2-6) • RXCREG (see Register 2-7) • PLLCREG (see Register 2-17) Preliminary MRF49XA DS70590B-page 49 ...
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FIGURE 3-6: AFC CIRCUIT FOR FREQUENCY OFFSET CORRECTION Baseband Signal IN FINE HAM SEL MHz CLK /4 11 MUX Enable Calculation FIFOEN DIO Auto Operation AUTOMS<1:0> POR Range Limit ARFO<1:0> Strobe MFCS Output Enable FOREN FREQB<11:0> Parameter ...
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... Microchip Technology Inc. 3.9 Interrupts The advanced interrupt handler circuit is implemented in the MRF49XA to reduce the power consumption. As mentioned, the Sleep mode is the lowest power consumption mode in which the mode clock and all functional blocks of the chip are disabled. However, the WUT and LBD circuits can be active if enabled ...
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... MRF49XA 3.9.1 SETTING INTERRUPTS The device’s interrupt pin (IRO) signals one of eight interrupt events to the host microcontroller. The inter- rupt source in the microcontroller is read out from the transceiver through the SDO pin. The interrupt sources that are available are briefly described in the following subsections ...
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... MRF49XA from Sleep mode. This means that the crystal oscillator starts to supply a clock signal to the microcontroller even if the microcontroller has its own clock source. The MRF49XA will not enter Sleep mode if any of the interrupt remains active, irrespective of the FIGURE 3-7: MRF49XA INTERRUPT GENERATION LOGIC ...
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... MRF49XA 3.10 Baseband/Data Filtering The baseband receiver has several programming options to optimize the communication for a wide range of applications. The programmable functions are as follows: • Baseband Analog Filter • Baseband Digital Filter • Receive Bandwidth • Receive Data Rate • Clock Recovery ...
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... Fast mode. The registers associated with baseband filtering are: • STSREG (see Register 2-1) • RXCREG (see Register 2-7) • BBFCREG (see Register 2-8) • PMCREG (see Register 2-13) Preliminary MRF49XA Frequency TX Center Freq. DS70590B-page 55 ...
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... MRF49XA 3.11 Data Quality Indicator The Data Quality Indicator (DQI) is the digital process- ing part of the radio connected to the demodulator and functions when the receiver is on. This reports the reception of an FSK modulated RF signal. The DQI parameter setting defines how clean the incoming data stream would be stated as good data (valid FSK signal) ...
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... RSSI output voltage versus signal strength. The analog RSSI level is linear with input signal levels between -103 and -73 dBm. The RSSIO pin in MRF49XA is used as an analog RSSI output and better results can be achieved by using this pin with a sensitive comparator. These bits can be set to indicate the incoming signal strength above a preset limit. The result enables or disables the DQDO bit (STSREG< ...
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... MRF49XA TABLE 3-2: DIGITAL RSSI THRESHOLD LEVELS RSSI Threshold Reserved Reserved -73 -79 -85 -91 -97 -103 FIGURE 3-11: INPUT POWER -112 -102 -92 3.13.1 RELATIONSHIP BETWEEN RSSI AND CLOCK RECOVERY The DIO signal response time setting is configured through RXCREG and has the following modes of operation: • ...
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... If the receiver or the transmitter is frequently used recommended to leave the oscillator running as the crystal might need a few milliseconds to start. The start timing mainly depends on the crystal parameters. Leaving blocks unnecessarily turned on Note: increases the current consumption, and thus, decreases the battery life. for Preliminary MRF49XA DS70590B-page 59 ...
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... MRF49XA From PMCREG, the following points are applicable when using the bit functionalities: • The chip enters Receive mode if both the TXCEN and RXCEN bits are set. • FSK/DATA/FSEL input is equipped with an internal pull-up resistor. To achieve minimum current consumption, do not pull this input to logic low in Sleep mode. • ...
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FIGURE 3-12: LOGIC CONNECTIONS BETWEEN POWER CONTROL BITS Enable Power Amplifier TXCEN Start TX Edge Detector Clear TX Latch (If TX latch is used) Enable RF SYNEN Synthesizer (Crystal Synthesizer must be ON) Enable RF Front RXCEN End Enable Baseband ...
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... Selecting a short on-time can prevent the crystal oscilla- tor from starting, or the DQI signal will not go high even when the received signal has a good quality. The MRF49XA is normally configured to work in FIFO mode. However, when the device periodically wakes up from Sleep mode, it switches to the Receive mode. If valid FSK data is received, the device sends an interrupt to the microcontroller and continues filling the RXFIFO ...
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... RF and baseband circuitry. Data is retained in the control and FIFO registers and the transceiver is accessible via the SPI port. The MRF49XA will not enter Sleep mode if any of the interrupt remains active, irrespective of the state of the OSCEN bit in the PMCREG. This way, the micro- controller can always have a clock signal to process the interrupt ...
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... MRF49XA 3.17 TX Register Buffered Data Transmission In Data Transmission mode (enabled by the TXDEN bit (GENCREG<7>)), the TX data is clocked into one of the two 8-bit data registers. The transmitter starts to send the data from the first register (with the given bit rate) when the TXCEN bit (PMCREG<5>) is set. The initial value of the data registers (0xAA) can be used to generate preamble ...
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... SEL Y 10 SCLK 11 MUX Serial Bus Data © 2009 Microchip Technology Inc. SDI SDO 8-Bit Shift Register CLK SDI SDO 8-Bit Shift Register CLK Note: The data registers’ content is initialized by clearing the TXCEN bit. Preliminary MRF49XA SEL TX_DATA MUX DS70590B-page 65 ...
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... MRF49XA The device transmit sequence should be performed as follows: 1. Enable the TX register by setting TXDEN = 1. 2. The TX register is automatically filled with 0xAAAA, which can be used to generate preamble. 3. Enable the transmitter by setting TXCEN = 1. 4. The synthesizer and the PLL turns on, calibrates itself and the power amplifier is automatically enabled ...
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... Do not switch the TXCEN off here, because the TX Byte 1 is not transmitted out only stored in the internal register PMCREG TX Latch TX Latch Dummy TXCEN = 1 TX Byte 1 TX Byte Synt. PA (1) tx_xtal_on 0xAA 0xAA TX Byte1 TX BYTE 2 TX BYTE 1 Preliminary MRF49XA PMCREG GENCREG TXCEN = 0 TXDEN = 0 Fraction of the dummy byte TX BYTE n DS70590B-page 67 ...
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... MRF49XA 3.18 RX FIFO Buffered Data Read In the Receive Operating mode, the incoming data is clocked into a 16-bit FIFO buffer. The receive pin func- tion configuration required for the FIFO operation is given in Table 3-4. The FIFOEN bit is in the GENCREG register and enables the receive FIFO. The receiver ...
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... The registers associated with reception are: • STSREG (see Register 2-1) cannot be is the crystal • GENCREG (see Register 2-2) • RXCREG (see Register 2-7) • FIFORSTREG (see Register 2-10) . ref • PMCREG (see Register 2-13) Preliminary MRF49XA Pin 7 RX Data Clock Output FINT Output DS70590B-page 69 ...
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... MRF49XA 3.19 RX-TX Frequency Alignment Method The RX-TX frequency offset occurs due to the differ- ences in the actual reference frequency. To minimize this error, the same crystal type and the same PCB layout should be used for the crystal placement on the RX and TX PCBs. Also, see Section 3.6 “Crystal Selection Guidelines” ...
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... APPLICATION DETAILS The application circuit of MRF49XA with a balun circuit is shown in Figure 4-1. FIGURE 4-1: APPLICATION CIRCUIT ® tio tio 4.1 Antenna/Balun A balun circuit for a 50Ω antenna is shown in Figure 4-2. If low tolerance components (i.e., ±5%) are used with an appropriate ground, the impedance remains close to the 50Ω ...
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... MRF49XA 4.2 Antenna Design Considerations The MRF49XA is designed to drive a differential output, such as a dipole antenna or a loop antenna. The loop antenna is ideally suited for applications where com- pact size is required. The dipole is typically not a good option for compact designs due to its inherent size at resonance, and its space requirements around the ground plane efficient antenna ...
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... High value decoupling capacitors, typically 2.2-10 μF, should be placed at the point where power is applied to the PCB. • Power supply bypassing is necessary. Poor bypassing contributes to conducted interference which can cause noise and spurious signals to couple into the RF sections, significantly reducing performance. Preliminary MRF49XA of the chip DD DS70590B-page 73 ...
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... MRF49XA 4.5 MRF49XA Schematic and Bill of Materials 4.5.1 SCHEMATIC FIGURE 4-5: MRF49XA SCHEMATIC RSSIO C4 1000 pF INT/DIO U1 MRF49XA SDI SDI INT/DIO 2 15 SCK SCK RSSIO VDD 4 13 SDO SDO RFN IRO IRO RFP 6 11 ___ __ FSEL FSK/DATA/ FSEL VSS 7 10 ____ FINT ...
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... SMT 5 x 3.2 mm © 2009 Microchip Technology Inc. Description Manufacturer Murata Murata Murata Murata Murata TDK Corporation MLG1608B33NJ TDK Corporation MLG1608B47NJ Murata Murata Kemet Microchip Abracon Preliminary MRF49XA Manufacturer PN GRM1885C1H201JA01D GRM1885C1H2R7CZ01D GRM1885C1H680JA01D GRM1885C1H5R1DZ01D LQW18ANR39J00D GRM188R71H102KA01D GRM188R71H103KA01D T491A225K010AT MRF49XA-I/ST ABM3B-10.000MHZ-12-R8 0-B-1-U-T DS70590B-page 75 ...
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... SMT 5 x 3.2 mm DS70590B-page 76 Description Manufacturer Murata Murata Murata Murata TDK Corporation MLG1608BR10J TDK Corporation MLG1608B8N2D TDK Corporation MLG1608B22NJ Murata Murata Kemet Microchip Abracon Preliminary Manufacturer PN GRM1885C1H330JA01D GRM1885C1H1R2CZ01D GRM1885C1H270JA01D GRM1885C1H2R7CZ01D GRM188R71H102KA01D GRM188R71H103KA01D T491A225K010AT MRF49XA-I/ST ABM3B-10.000MHZ-12-R80- B-1-U-T © 2009 Microchip Technology Inc. ...
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... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. SS (1) ........................................................................... -0. ).......................................................................................... - Preliminary MRF49XA + 0.3V 1.5V) DD DS70590B-page 77 ...
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... MRF49XA TABLE 5-1: RECOMMENDED OPERATING CONDITIONS Parameters Operating Temperature Supply Voltage for RF, Analog and Digital Circuits Supply Voltage for Digital I/O DC Voltage on Open-Collector Outputs (1,2) (RFP, RFN) AC Peak Voltage on Open-Collector (1) Outputs (RFP, RFN) At minimum, V – 1.5V cannot be lower than 1.2V. Note 1: ...
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... Local Oscillator Frequency = 2.445 GHz. DD Preliminary MRF49XA Typ Max Unit -112 — dBm -110 — dBm -109 — dBm — — dBm 1 — pF — ...
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... MRF49XA TABLE 5-5: TRANSMITTER AC CHARACTERISTICS Parameters RF Carrier Frequency 433 MHz band, 2.5 kHz resolution 868 MHz band, 5.0 kHz resolution 915 MHz band, 7.5 kHz resolution Maximum RF Output Power 433 MHz @ 50Ω load 868 MHz @ 50Ω load 915 MHz @ 50Ω load ...
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... Microchip Technology Inc. Condition Min — — — — 8.5 — (2) has reached 90% of the — DD (3) — (2) — — — = 3.3V. DD Preliminary MRF49XA (1) Typ Max Unit μs 250 — μs 250 — μs 150 — μs 150 — — — ...
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... MRF49XA 5.1 Timing Specification and Diagram TABLE 5-8: SPI TIMING SPECIFICATION Symbol t Clock High Time CH t Clock Low Time CL t Select Setup Time (CS falling edge to SCK rising edge Select Hold Time (SCK falling edge to CS rising edge Select High Time SHI ...
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... LNA gain maximum, filter bandwidth 67 kHz, data rate 9.6 kbps, AFC switched off, FSK Note 1: deviation ± 45 kHz, V The ETSI limit given in the figure is drawn by taking -106 dBm at 9.6 kbps typical sensitivity 2: into account and corresponds to receiver class 2 requirements. © 2009 Microchip Technology Inc. (1, 2.7V. DD Preliminary MRF49XA 434 MHz 868 MHz ETSI 11 12 DS70590B-page 83 ...
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... MRF49XA FIGURE 5-3: BER CURVES IN 433 MHz BAND -120 -115 FIGURE 5-4: BER CURVES IN 868 MHz BAND -115 -110 DS70590B-page 84 BER Curves in 433 MHz Band -110 -105 -100 -95 Input Power (dBm) BER Curves in 868 MHz Band -105 -100 -95 -90 Input Power (dBm) Preliminary 1 ...
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... BW – – – 67 Δf Δf – 45 – 45 – 45 FSK FSK FSK Preliminary MRF49XA 38.4 kbps 57.6 kbps 115.2 kbps BW – 134 BW – 134 BW – 200 Δf Δf Δf – 90 – 90 – 120 FSK FSK FSK ...
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... MRF49XA FIGURE 5-5: RECEIVER SENSITIVITY OVER AMBIENT TEMPERATURE (433 MHz, 2.4 kbps, Receiver Sensitivity over Ambient Temperature for 433 MHz -100 -103 -106 -109 -112 -115 -50 -25 FIGURE 5-6: RECEIVER SENSITIVITY OVER AMBIENT TEMPERATURE (868 MHz, 2.4 kbps, Receiver Sensitivity over Ambient Temperature for 868 MHz ...
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... In the event, the full Microchip part number cannot be marked on one line, it Note: will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. Example 49XA/ST 0910 Preliminary MRF49XA e 3 017 ) e 3 DS70590B-page 87 ...
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... MRF49XA 6.2 Package Details This section provides the technical details of the packages. 16-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70590B-page 88 Preliminary © 2009 Microchip Technology Inc. ...
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... Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009 Microchip Technology Inc. Preliminary MRF49XA DS70590B-page 89 ...
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... MRF49XA 16-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70590B-page 90 Preliminary © 2009 Microchip Technology Inc. ...
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... Status Bits Out (1,2,3) FIFO ATRS OFFSB DQDO CLKRL AFCCT OFFSV EM SI <3> (Sign) Synchronous Word/Network ID 0xD4 (programmable) 0x2DD4 (D4 is programmable) Preliminary MRF49XA FIFO Out OFFSB OFFSB OFFSB FO FO+1 FO+2 <2> <1> <0> Payload CRC — 4-bit-1 byte — 2 bytes DS70590B-page 91 ...
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... MRF49XA NOTES: DS70590B-page 92 Preliminary © 2009 Microchip Technology Inc. ...
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... APPENDIX B: REVISION HISTORY Revision A (March 2009) This is the initial released version of this document. Revision B (June 2009) Major updates are done throughout the document. © 2009 Microchip Technology Inc. Preliminary MRF49XA DS70590B-page 93 ...
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... MRF49XA NOTES: DS70590B-page 94 Preliminary © 2009 Microchip Technology Inc. ...
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... Application Circuit ....................................................... 71 Balun Circuit................................................................ 71 DIO Logic .................................................................... 56 Four Basic Copper FR4 Layers .................................. 72 Functional Node............................................................ 6 Logic Connection Between Power Control Bits .......... 61 MCU to MRF49XA Interface ......................................... 6 MRF49XA Architectural ................................................ 8 MRF49XA Interrupt Generation Logic......................... 53 RESET Pin Internal Connection.................................. 45 Two Basic Copper FR4 Layers ................................... 72 TX Register Before Transmit ...................................... 64 TX Register During Transmit ...
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... Revision History.................................................................. 93 RF Crystal........................................................................... 10 RF Transmitter Matching .................................................... 72 RF/Analog Features.............................................................. 1 RX FIFO Buffered Data Read............................................. 68 RX-TX Frequency Alignment Method ................................. 70 S Schematics MRF49XA ................................................................... 74 Serial Peripheral Interface (SPI) ......................................... 15 Sleep, Wake-up and Battery Operations ............................ 63 SPI Timing Specification.................................................... 82 Synchronous Character Selection ...................................... 33 T Timing Diagrams FIFO Read with FINT Polling...................................... 69 FSK Modulated Deviation (Max ...
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... Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com Preliminary MRF49XA should contact their distributor, DS70590B-page 97 ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: MRF49XA Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
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... C to +85 ° C (Industrial) Temperature Range I Package ST = TSSOP (Lead Plastic Thin Shrink Small Outline, No Lead Tape and Reel © 2009 Microchip Technology Inc. XXX Example: a) MRF49XA-I/ST: Industrial temperature, Pattern TSSOP package. b) MRF49XAT-I/ST: Industrial temperature, TSSOP package, tape and reel. Preliminary MRF49XA . DS70590B-page 99 ...
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... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...