MRF49XA-I/ST Microchip Technology, MRF49XA-I/ST Datasheet - Page 55

IC RF TXRX 433/868/915 16-TSSOP

MRF49XA-I/ST

Manufacturer Part Number
MRF49XA-I/ST
Description
IC RF TXRX 433/868/915 16-TSSOP
Manufacturer
Microchip Technology
Datasheet

Specifications of MRF49XA-I/ST

Package / Case
16-TSSOP
Frequency
433MHz, 868MHz, 915MHz
Data Rate - Maximum
256kbps
Modulation Or Protocol
FHSS, FSK
Applications
Home / Industrial Automation, Remote Access, Security Alarms
Power - Output
7dbm
Sensitivity
-110dBm
Voltage - Supply
2.2 V ~ 3.8 V
Current - Receiving
11mA
Current - Transmitting
15mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Number Of Receivers
1
Number Of Transmitters
2
Wireless Frequency
433 MHz to 915 MHz
Output Power
+ 7 dBm
Operating Supply Voltage
2.5 V, 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Modulation
FHSS, FSK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
579-MRF49XA-1/ST

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MRF49XA-I/ST
Manufacturer:
IR
Quantity:
450
Part Number:
MRF49XA-I/ST
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
3.9.2.3
1.
2.
3.9.2.4
The IRO pin and its status bit are cleared by reading the
STSREG.
3.9.2.5
The IRO pin and its status bit follow the level of the INT pin.
3.9.2.6
The IRO pin is released by reading the status bit of
STSREG, but the status bit remains active until the V
is below the threshold value.
The MRF49XA interrupt generation logic is shown in
Figure 3-7. A better way of interrupt handling is to first
read the STSREG on an interrupt and then decide the
action based on the status byte/word. It is important to
note that any of the interrupt sources can wake-up the
MRF49XA from Sleep mode. This means that the
crystal oscillator starts to supply a clock signal to the
microcontroller even if the microcontroller has its own
clock source. The MRF49XA will not enter Sleep mode
if any of the interrupt remains active, irrespective of the
FIGURE 3-7:
© 2009 Microchip Technology Inc.
Transmit mode
In this mode, the TXOWRXOF and TXRXFIFO
bits are always set together. The IRO pin and its
status bit remain active until the transmitter and
the TX latch are switched off.
Receive mode
In this mode, the TXOWRXOF and TXRXFIFO
bits are always set together and can be cleared
by reading the STSREG. The IRO pin and its
status bit remain active until the FIFO is read (a
FIFO interrupt threshold number of bits have
been read), the receiver is switched off or the
RX FIFO is switched off.
TXOWRXOF
WUTINT
LCEXINT
LBTD
MRF49XA INTERRUPT GENERATION LOGIC
LCEXINT (INT)
TXOWRXOF
TXOWRXOF
TXRXFIFO
TXRXFIFO
(Ext./Int.)
FINTDIO
W UTINT
W UTEN
RXCEN
RXCEN
TXCEN
TXCEN
RESET
LBDEN
LBTD
Preliminary
DD
state of the OSCEN bit in PMCREG. This way, the
microcontroller can always have a clock signal to
process the interrupt.
To prevent high-current consumption, which results in
short battery life, it is highly recommended to process
and clear interrupts before entering Sleep mode. The
functions which are not necessary should be turned off
to avoid unwanted interrupts. Before finalizing the micro-
controller (application) code, a thorough testing must be
conducted to make sure that all interrupt sources are
handled before putting the transceiver in Sleep mode.
The OSCEN bit controls the crystal oscillator (consider-
ing that the RXCEN and TXCEN bits are cleared) if the
CLKOEN bit (PMCREG<0>) is set. The interrupts have
no effect on it.
On interrupt, the crystal oscillator turns on automatically
to supply a clock signal to the microcontroller, irrespec-
tive of the OSCEN bit setting. The clock tail feature
provides sufficient clock pulses for the microcontroller to
enter the Low-Power Consumption mode. Due to this
automatic feature, it is not possible to turn off the crystal
by clearing the OSCEN bit if any interrupt is active.
For example, after power-on, the POR interrupt must
be cleared by a status read, and then by writing ‘0’ in
the OSCEN bit, puts the device into Sleep mode.
The registers associated with interrupts are:
• STSREG (see Register 2-1)
• GENCREG (see Register 2-2)
• RXCREG (see Register 2-7)
• PMCREG (see Register 2-13)
• BCSREG (see Register 2-16)
Note:
Before turning the OSCEN bit off, clear all
the interrupts, because the additional cur-
rent required for running the crystal oscillator
can shorten the battery life significantly.
IRO
MRF49XA
DS70590B-page 53

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