MRF49XA-I/ST Microchip Technology, MRF49XA-I/ST Datasheet - Page 70

• Manufacturer Part Number: MRF49XA-I/ST
• Description: IC RF TXRX 433/868/915 16-TSSOP
• Manufacturer: Microchip Technology

Specifications of MRF49XA-I/ST

• Package / Case: 16-TSSOP
• Frequency: 433MHz, 868MHz, 915MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FHSS, FSK
• Applications: Home / Industrial Automation, Remote Access, Security Alarms
• Power - Output: 7dbm
• Sensitivity: -110dBm
• Voltage - Supply: 2.2 V ~ 3.8 V
• Current - Receiving: 11mA
• Current - Transmitting: 15mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 2
• Wireless Frequency: 433 MHz to 915 MHz
• Output Power: + 7 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Modulation: FHSS, FSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 579-MRF49XA-1/ST

3.18
In the Receive Operating mode, the incoming data is
clocked into a 16-bit FIFO buffer. The receive pin func-
tion configuration required for the FIFO operation is
given in Table 3-4. The FIFOEN bit is in the GENCREG
register and enables the receive FIFO. The receiver
starts to fill the FIFO when the FINTDIO bit and the
synchronous pattern recognition circuit indicates the
potential real incoming data. This prevents the FIFO
from being filled with noise and avoids the overloading
on the external microcontroller.
FIGURE 3-18:
DS70590B-page 68
MRF49XA
SCK
CS
SDI
SDO
Note: The transceiver is in Receive (RX) mode when the RXCEN bit is set using the PMCREG.
RX FIFO Buffered Data Read
0
1
RECEIVER FIFO READ
2
(TX/RX mode)
TXRXFIFO
3
4
5
6
7
Preliminary
MSB
8
9
The internal synchronous pattern and the pattern
length are user-programmable. If the Chip Select (CS)
pin is low, the data bits on the SDI pin are shifted into
the device on the rising edge of the clock on the SCK
pin. The serial interface is initialized every time if the
CS signal is high. Figure 3-18 shows a simple receiver
FIFO read over SPI lines.
10
11
Received Bits Out
12
13
14
© 2009 Microchip Technology Inc.
15
LSB