IC RF TXRX ZIGBEE 192KB 48QFN

EM357-RTR

Manufacturer Part NumberEM357-RTR
DescriptionIC RF TXRX ZIGBEE 192KB 48QFN
ManufacturerEmber
EM357-RTR datasheets
 

Specifications of EM357-RTR

Frequency2.4GHzData Rate - Maximum250kbps
Modulation Or Protocol802.15.4 ZigbeeApplicationsGeneral Purpose
Power - Output5dBmSensitivity-100dBm
Voltage - Supply2.1 V ~ 3.6 VCurrent - Receiving26mA
Current - Transmitting31mAData InterfacePCB, Surface Mount
Memory Size192kB Flash, 12kB RAMAntenna ConnectorPCB, Surface Mount
Operating Temperature-40°C ~ 85°CPackage / Case48-QFN
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names636-1011-2
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EM351 / EM357
High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
Complete System-on-Chip
32-bit ARM
2.4 GHz IEEE 802.15.4-2003 transceiver & lower
MAC
128 or 192 kB flash, with optional read
protection
12 kB RAM memory
AES128 encryption accelerator
Flexible ADC, UART/SPI/TWI serial
communications, and general purpose timers
24 highly configurable GPIOs with Schmitt
trigger inputs
Industry-leading ARM
Leading 32-bit processing performance
Highly efficient Thumb-2 instruction set
Operation at 6, 12, or 24 MHz
Flexible Nested Vectored Interrupt Controller
Low power consumption, advanced management
Rx Current (w/ CPU): 26 mA
Tx Current (w/ CPU, +3 dBm TX): 31 mA
Low deep sleep current, with retained RAM and
GPIO: 400 nA without/800 nA with sleep timer
Low-frequency internal RC oscillator for low-
power sleep timing
High-frequency internal RC oscillator for fast
(110 µsec) processor start-up from sleep
Ember Corporation
25 Thomson Place
Boston MA 02210 USA
+1 617.951.0200
www.ember.com
120-035X-000G
Final
March 20, 2011
®
Cortex™-M3 processor
®
Cortex
-M3 processor
PA select
RF_TX_ALT_P,N
PA
SYNTH
DAC
PA
RF_P,N
LNA
ADC
IF
Bias
OSCA
HF crystal
Internal HF
Calibration
OSC
RC-OSC
ADC
OSCB
1.25V
VDD_CORE
Regulator
1.8V
VREG_OUT
Regulator
General
Purpose
nRESET
POR
ADC
LF crystal
Internal LF
OSC
RC-OSC
GPIO multiplexor switch
PA[7:0], PB[7:0], PC[7:0]
Exceptional RF Performance
Normal mode link budget up to 103 dB;
configurable up to 110 dB
-100 dBm normal RX sensitivity;
configurable to -102 dBm
(1% PER, 20 byte packet)
+3 dB normal mode output power;
configurable up to +8 dBm
Robust Wi-Fi and Bluetooth coexistence
Innovative network and processor debug
Ember InSight port for non-intrusive
packet trace with Ember InSight tools
Serial Wire/JTAG interface
Standard ARM debug capabilities: Flash
Patch & Breakpoint; Data Watchpoint &
Trace; Instrumentation Trace Macrocell
Application Flexibility
Single voltage operation: 2.1-3.6 V
with internal 1.8 V and 1.25 V regulators
Optional 32.768 kHz crystal for higher
timer accuracy
Low external component count with
single 24 MHz crystal
Support for external power amplifier
Small 7x7 mm 48-pin QFN package
TX_ACTIVE
Data
Program
RAM
Flash
12 kB
128/192 kB
MAC
+
Baseband
®
nd
ARM
Cortex
TM
-M3
2
level
CPU with NVIC
Interrupt
and MPU
controller
Packet Trace
CPU debug
Encryption
TPIU/ITM/
acclerator
FPB/DWT
General
purpose
Always
timers
Powered
Serial
SWCLK,
Domain
Wire and
JTCK
GPIO
JTAG
registers
Watchdog
debug
UART/
SPI/TWI
Chip
Sleep
manager
timer

EM357-RTR Summary of contents

  • Page 1

    ... EM351 / EM357 High-Performance, Integrated ZigBee/802.15.4 System-on-Chip Complete System-on-Chip • 32-bit ARM • 2.4 GHz IEEE 802.15.4-2003 transceiver & lower MAC • 128 or 192 kB flash, with optional read protection • RAM memory • AES128 encryption accelerator • Flexible ADC, UART/SPI/TWI serial communications, and general purpose timers • ...

  • Page 2

    ... The EM351 has 128 kB of embedded flash memory and the EM357 has 192 kB of embedded flash memory. Both chips have integrated RAM for data and program storage. The Ember software for the EM35x employs an effective wear-leveling algorithm that optimizes the lifetime of the embedded flash ...

  • Page 3

    ... Internally regulated power 6-2 Externally regulated power 6-2 6-3 Reset Sources 6-3 Reset Recording 6-5 Final EM351 / EM357 Datasheet 6.2.3 Reset Generation Module 6.3 Clocks 6.3.1 High-Frequency Internal RC Oscillator (OSCHF) 6.3.2 High-Frequency Crystal Oscillator (OSC24M) 6.3.3 Low-Frequency Internal RC Oscillator (OSCRC) 6 ...

  • Page 4

    ... One-Pulse Mode 9.3.11 Encoder Interface Mode 9.3.12 Timer Input XOR Function 9-22 9.3.13 Timers and External Trigger Synchronization 9.3.14 Timer Synchronization 9.3.15 Timer Signal Descriptions EM351 / EM357 Datasheet 8-7 9.4 Interrupts 8-8 9.5 Registers 8-9 10 ADC (Analog to Digital 8-10 Converter) 8-14 10 ...

  • Page 5

    ... Appendix B Abbreviations and Acronyms Appendix C References EM351 / EM357 Datasheet B-1 C-1 Final 120-035X-000G ...

  • Page 6

    ... Figure 1-1. EM35x Pin Assignments GND 1-1 Final EM351 / EM357 36 PB0, VREF, IRQA, TRACECLK, TIM1CLK, TIM2MSK 35 PC4, JTMS, SWDIO 34 PC3, JTDI 33 PC2, JTDO, SWO SWCLK, JTCK 32 31 PB2, SC1MISO, SC1MOSI, SC1SCL, SC1RXD, TIM2C2 30 PB1, SC1MISO, SC1MOSI, SC1SDA, SC1TXD, TIM2C1 29 PA6, TIM1C3 28 VDD_PADS 27 ...

  • Page 7

    ... Disable REG_EN with GPIO_DBGCFG[4] Timer 1 Channel 4 output Enable timer output with TIM1_CCER Select alternate output function with GPIO_PACFGH[15:12] Disable REG_EN with GPIO_DBGCFG[4] Timer 1 Channel 4 input Cannot be remapped External regulator open drain output Enabled after reset Digital I/O 1-2 Final EM351 / EM357 120-035X-000G ...

  • Page 8

    ... SPI slave select of Serial Controller 1 Enable slave with SC1_SPICFG[4] Select SPI with SC1_MODE Digital I/O Timer 2 channel 1 output Disable remap with TIM2_OR[4] Enable timer output in TIM2_CCER Select alternate output function with GPIO_PACFGL[3:0] Timer 2 channel 1 input Disable remap with TIM2_OR[4] 1-3 Final EM351 / EM357 120-035X-000G ...

  • Page 9

    ... Select alternate output function with GPIO_PACFGL[11:8] Timer 2 channel 4 input Disable remap with TIM2_OR[7] TWI clock of Serial Controller 2 Either disable timer output in TIM2_CCER, or enable remap with TIM2_OR[7] Select TWI with SC2_MODE Select alternate open-drain output function with GPIO_PACFGL[11:8] 1-4 Final EM351 / EM357 120-035X-000G ...

  • Page 10

    ... Disable trace interface in ARM core Enable PTI in Ember software Select alternate output function with GPIO_PACFGH[7:4] Embedded serial bootloader activation out of reset Signal is active during and immediately after a reset on nRESET. See Section 6.2, Resets, in Chapter 6, System Modules for details. 1-5 Final EM351 / EM357 120-035X-000G ...

  • Page 11

    ... Enable remap with TIM2_OR[4] Enable timer output in TIM2_CCER Select alternate output function with GPIO_PACFGL[7:4] Timer 2 channel 1 input Disable remap with TIM2_OR[4] Digital I/O SPI master data in of Serial Controller 1 Select SPI with SC1_MODE Select master with SC1_SPICR 1-6 Final EM351 / EM357 120-035X-000G ...

  • Page 12

    ... Internal pull-up is enabled Digital I/O Either Enable with GPIO_DBGCFG[5], or enable Serial Wire mode (see JTMS description) JTAG data in from debugger Selected when in JTAG mode (default mode, see JTMS description, Pin 35) Internal pull-up is enabled Digital I/O Enable with GPIO_DBGCFG[5] 1-7 Final EM351 / EM357 120-035X-000G ...

  • Page 13

    ... Either enable with GPIO_DBGCFG[5], or enable Serial Wire mode (see JTMS description, Pin 35) and disable TRACEDATA1 JTAG reset input from debugger Selected when in JTAG mode (default mode, see JTMS description) and TRACEDATA1 is disabled Internal pull-up is enabled Default external interrupt source D 1-8 Final EM351 / EM357 120-035X-000G ...

  • Page 14

    ... MHz crystal oscillator or left open when using external clock input on OSCA 24 MHz crystal oscillator or external clock input. External clock input is a 1.8 V square wave. Ground supply pad in the bottom center of the package forms Pin 49. See Ember’s various EM35x Reference Design documentation for PCB considerations. 1-9 Final EM351 / EM357 120-035X-000G ...

  • Page 15

    ... Core input voltage when supplied externally (VDD_CORE) Operating temperature range Table 2-1. Absolute Maximum Ratings Test Conditions RX signal into a lossless balun Table 2-2. Operating Conditions Test Conditions 2-1 Final EM351 / EM357 Min. Max. Unit -0.3 +3.6 V -0.3 +2.0 V -0.3 +3 ...

  • Page 16

    ... VDD_PADS=3.6 V +25°C, VDD_PADS=3.6 V +85°C, VDD_PADS=3.6 V -40°C, VDD_PADS=3.6 V +25°C, VDD_PADS=3.6 V +85°C, VDD_PADS=3.6 V -40°C, VDD_PADS=3.6 V +25°C, VDD_PADS=3.6 V +85°C, VDD_PADS=3.6 V With no debugger activity 2-2 Final EM351 / EM357 Min. Typ. Max. Unit ±2 kV ±400 V ±225 V MSL3 Min ...

  • Page 17

    ... VDD_PADS=3.0 V ® TM ARM Cortex -M3 running at 24 MHz 25°C, VDD_PADS=3.0 V ® TM ARM Cortex -M3 running at 12 MHz 25°C, VDD_PADS=3.0 V ® TM ARM Cortex -M3 running at 24 MHz 2-3 Final EM351 / EM357 Min. Typ. Max. Unit 1.2 2.0 mA 6.5 mA 7.5 mA 3.0 mA 2.0 mA 0.2 mA 0. ...

  • Page 18

    ... ARM Cortex -M3 running at 24 MHz 25°C, VDD_PADS=3 dBm power ® TM setting; ARM Cortex -M3 running at 24 MHz 25°C, VDD_PADS=3.0 V; minimum power ® TM setting; ARM Cortex -M3 running at 24 MHz 2-4 Final EM351 / EM357 Min. Typ. Max. Unit 26.0 mA 42.5 mA 30.0 mA 27.5 mA 21 ...

  • Page 19

    ... Figure 2-1 shows the variation of current in transmit mode (with the ARM Figure 2-1. Transmit Power Consumption ® Cortex 2-5 Final EM351 / EM357 TM -M3 running at 12 MHz). 120-035X-000G ...

  • Page 20

    ... Figure 2-2. Transmit Output Power Table 2-5. Digital I/O specifications Test Conditions V SWIL Schmitt input threshold going from high to low V SWIH Schmitt input threshold going from low to high 2-6 Final EM351 / EM357 Min. Typ. Max. Unit 2.1 3.6 V 0. VDD_PADS VDD_PADS 0. VDD_PADS VDD_PADS -0 ...

  • Page 21

    ... Schmitt input threshold going from high to low V SWIH Schmitt input threshold going from low to high IPU Pull-up value while the chip is not reset R IPURESET Pull-up value while the chip is reset 2-7 Final EM351 / EM357 Min. Typ. Max. Unit kΩ kΩ VDD_PADS 0.82 x ...

  • Page 22

    ... IEEE 802.15.4-2003 interferer signal, wanted IEEE 802.15.4-2003 signal at -82 dBm Filtered IEEE 802.15.4-2003 interferer signal, wanted IEEE 802.15.4-2003 signal at -82 dBm Filtered IEEE 802.15.4-2003 interferer signal, wanted IEEE 802.15.4-2003 signal at -82 dBm 2-8 Final EM351 / EM357 Min. Typ. Max. TM -M3 110 5 Min ...

  • Page 23

    ... IEEE 802.15.4-2003 interferer signal, wanted IEEE 802.15.4-2003 signal at -82 dBm IEEE 802.15.4-2003 interferer signal, wanted IEEE 802.15.4-2003 signal at -82 dBm IEEE 802.15.4-2003 interferer signal, wanted IEEE 802.15.4-2003 signal at -82 dBm As defined by IEEE 802.15.4-2003 2-9 Final EM351 / EM357 Min. Typ. Max. Unit ...

  • Page 24

    ... A0) at 2440 MHz. The Typical number indicates one standard deviation below the mean, measured at room temperature (25°C). The Min and Max numbers were measured over process corners at room temperature. In terms of impedance, this reference design presents a 3n3 inductor in parallel with a 100:50 Ω balun to the RF pins. 2-10 Final EM351 / EM357 120-035X-000G ...

  • Page 25

    ... At highest boost mode power setting (+8) At highest normal mode power setting (+3) At lowest power setting As defined by IEEE 802.15.4-2003, which sets a 35% maximum 3.5 MHz away 3.5 MHz away Figure 2-4. Transmit power vs temperature 2-11 Final EM351 / EM357 Min. Typ. Max. Unit 8 dBm 1 5 dBm ...

  • Page 26

    ... Phase noise at 4 MHz offset Phase noise at 10 MHz offset Table 2-10. Synthesizer Characteristics Test Conditions From off Channel change or Rx/Tx turnaround (IEEE 802.15.4-2003 defines 192 μs turnaround time) 2-12 Final EM351 / EM357 Min. Typ. Max. Unit 2400 2500 MHz 11.7 kHz 100 μ ...

  • Page 27

    ... The EM35x integrates hardware support for a packet trace module, which allows robust packet-based debug. This element is a critical component of InSight Desktop, the Ember software IDE, and provides advanced network debug capability when used with Ember’s InSight Adapter. Figure 3-1. EM35x Block Diagram 3-1 Final EM351 / EM357 120-035X-000G ...

  • Page 28

    ... The processor can be operated at 12 MHz or 24 MHz when using the high-frequency crystal oscillator MHz or 12 MHz when using the high-frequency internal RC oscillator. The EM351 has 128 kB of flash memory and the EM357 has 192 kB of flash memory. Both chips have RAM on-chip, and the ARM configurable memory protection unit (MPU). ...

  • Page 29

    ... They can be used for external PA power management and RF switching logic. In transmit mode the Tx baseband drives TX_ACTIVE high, as described in Table 7-5, GPIO Signal Assignments. In receive mode the TX_ACTIVE signal is low. TX_ACTIVE is the alternate function of PC5, and 4-1 Final EM351 / EM357 120-035X-000G ...

  • Page 30

    ... The TRNG produces 16-bit uniformly distributed numbers. The Ember software uses the TRNG to seed a pseudo random number generator (PRNG). The TRNG is also used directly for cryptographic key generation. TM ® Cortex -M3 CPU interaction when transmitting or receiving packets. 4-2 Final EM351 / EM357 ® 120-035X-000G ...

  • Page 31

    ... ARM Ltd., making the ® Cortex TM -M3 clock speed is configurable to 6 MHz, 12 MHz MHz. For normal operation 24 MHz TM -M3 in the EM35x has also been enhanced to support two separate memory protection 5-1 Final EM351 / EM357 TM - advanced 32-bit modified Harvard ® 120-035X-000G ...

  • Page 32

    ... Figure 5-1 shows the EM351 ARM memory map. Optional boot mode maps Fixed Info Block to the start of memory Fixed Info Block (2kB) TM ® Cortex -M3 memory map and Figure 5-2 shows the EM357 ARM ® TM Figure 5-1. EM351 ARM Cortex -M3 Memory Map 0xE00FFFFF ROM table 0xE00FF000 ...

  • Page 33

    ... Figure 5-2. EM357 ARM 0xE00FFFFF 0xE00FF000 0xE0042000 0xE0041000 0xE0040000 0xE003FFFF 0xE000F000 0xE000E000 0xE0003000 0xE0002000 0xE0001000 0xE0000000 0x42002XXX Register bit band mapped onto System 0x42000000 0x40000XXX mapped onto System 0x40000000 0x22002000 mapped onto System 0x22000000 0x20002FFF mapped onto System 0x20000000 0x08040FFF Customer Info Block (2kB) ...

  • Page 34

    ... Flash Memory 5.2.1.1 Flash Overview The EM351 provides a total of 132 kB of flash memory and the EM357 provides a total of 196 kB of flash memory. The flash memory is provided in three separate blocks: Main Flash Block (MFB) Fixed Information Block (FIB) Customer Information Block (CIB) The MFB is divided into 2048-byte pages ...

  • Page 35

    ... The EM357 has 24 regions and therefore option bytes 4, 5, and 6 control flash write protection. These write protection bits are active low, and therefore the erased state of 0xFF disables write protection ...

  • Page 36

    ... Write protection of address range 0x0802A000 – 0x0802BFFF bit [6] Write protection of address range 0x0802C000 – 0x0802DFFF bit [7] Write protection of address range 0x0802E000 – 0x0802FFFF Option Byte 7 bit [7:0] Reserved for Ember use 1 Option byte 6 is reserved/unused in the EM351 due to the smaller flash size. 5-6 Final EM351 / EM357 120-035X-000G ...

  • Page 37

    ... The fine granularity RAM memory protection mechanism is also available to the peripheral DMA controllers. A register bit enables protection from DMA writes to protected memory DMA write is made to a protected location in RAM, a management interrupt is generated. At the same time the faulting address and the 5-7 Final EM351 / EM357 TM ® Cortex - ...

  • Page 38

    ... MPU configuration does not allow access to this alias address range. TM ® Cortex -M3 Memory Protection Unit, or MPU. The MPU controls access rights ® TM Cortex -M3 Technical Reference Manual (DDI 0337A) for a detailed description of the MPU. 5-8 Final EM351 / EM357 120-035X-000G ...

  • Page 39

    ... System Modules System modules encompass power domains, resets, clocks, system timers, power management, and encryption. Figure 6-1 shows these modules and how they interact. Figure 6-1. System Module Block Diagram 6-1 Final EM351 / EM357 120-035X-000G ...

  • Page 40

    ... When using an external regulator, the VREG_1V8 regulator output pin (VREG_OUT) must be left unconnected. When using an external regulator, this external nominal 1.8 V supply has to be connected to both VDD_CORE pins and to the VDD_MEM, VDD_PADSA, VDD_VCO, VDD_RF, VDD_IF, VDD_PRE and VDD_SYNTH pins. 6-2 Final EM351 / EM357 120-035X-000G ...

  • Page 41

    ... Reset Generation module, since the detection of either event needs to reset the same system modules. Table 6-1. POR HV Thresholds Test conditions From 0 1.7 V Table 6-2. POR LVcore Thresholds Test conditions Table 6-3 POR LVmem Thresholds Test conditions 6-3 Final EM351 / EM357 Min Typ Max Unit 0.62 0.95 1.20 V 0.45 ...

  • Page 42

    ... This input acts independently of all other reset sources and, when asserted, does not reset any on- chip hardware except for the JTAG TAP. If the EM35x is in the Serial Wire mode or if the SWJ is disabled, this input has no effect. rd failure. The system is then placed into an 6-4 Final EM351 / EM357 Min Typ Max Unit 2.1 12.0 16.0 µ ...

  • Page 43

    ... Peripheral reset for core power domain, for peripherals that are not required to retain LV their configuration across a deep sleep cycle ® Cortex TM TM ® Cortex -M3 CPU and ARM ® Cortex TM ® Cortex -M3 CPU without resetting the Core Debug and System Debug 6-5 Final EM351 / EM357 TM -M3 CPU -M3 System Debug components 120-035X-000G ...

  • Page 44

    ... Figure 6-2 shows a block diagram of the clocks in the EM35x. This simplified view shows all the clock sources and the general areas of the chip to which they are routed. Table 6-5. Generated Resets Reset Generation Module Output PORESET SYSRESET DAPRESET 6-6 Final EM351 / EM357 PRESET PRESET 120-035X-000G ...

  • Page 45

    ... Figure 6-2. Clocks Block Diagram 6-7 Final EM351 / EM357 120-035X-000G ...

  • Page 46

    ... RC oscillator as the main clock source, and a non-maskable interrupt (NMI) is signaled to the ARM TM Cortex -M3 NVIC. Table 6-7. High-Frequency Crystal Oscillator Specification Parameter Frequency Accuracy Duty cycle Start-up time at max bias Start up time at optimal bias Current consumption Test conditions Min 6-8 Final EM351 / EM357 Min Typ Max Unit MHz 0.3 MHz ® ...

  • Page 47

    ... The digital clock input signal must peak-to-peak sine wave with a DC bias of 0.5 V. Refer to Chapter 7, GPIO for GPIO configuration details. Using the low-frequency oscillator, crystal or digital clock, is enabled through Ember software. Test conditions +85 C 6-9 Final EM351 / EM357 Min Typ Max Unit 1 mA 100 Ω 10 ...

  • Page 48

    ... At 25°C, VDD_PADS=3.0 V Table 6-10. System Clock Modes SYSCLK PCLK Flash Program/Erase Inactive 12 MHz 6 MHz 6 MHz 12 MHz 6 MHz 12 MHz 24 MHz 12 MHz 12 MHz 24 MHz 12 MHz 24 MHz 6-10 Final EM351 / EM357 Typ Max Unit 32.768 kHz +100 ppm 100 kΩ 0.5 μA FCLK Flash Program/Erase ...

  • Page 49

    ... TM -M3 CPU lockup. By default disabled at power up of the always-on power domain. The ® standard system timer in the NVIC. The SysTick timer can be clocked from either 6-11 Final EM351 / EM357 TM ® Cortex -M3 NVIC ® ...

  • Page 50

    ... The Wakeup Recording module monitors all possible wakeup sources. More than one wakeup source may be recorded because events are continually being recorded (not just in deep-sleep) and another event may happen between the first wake event and when the EM35x wakes up. 6-12 Final EM351 / EM357 120-035X-000G ...

  • Page 51

    ... In the deep sleep state the EM35x waits for a wake up event which will return it to the running state. In powering up the core logic the ARM ® stack and application state to the point where deep sleep was invoked. TM Cortex -M3 is put through a reset cycle and Ember software restores the 6-13 Final EM351 / EM357 120-035X-000G ...

  • Page 52

    ... A debugger must logically communicate with the SWJ-DP to set or clear these two signals. For more information regarding the SWJ and the interaction of debuggers with deep sleep, contact Ember support for Application Notes and ARM ® TM CoreSight documentation. 6-14 Final EM351 / EM357 120-035X-000G ...

  • Page 53

    ... PERIPHERAL_DISABLE, the value of this bit must be preserved. RW Disable the clock to the ADC peripheral. RW Disable the clock to the TIM2 peripheral. RW Disable the clock to the TIM1 peripheral. RW Disable the clock to the SC1 peripheral. RW Disable the clock to the SC2 peripheral. 6-15 Final EM351 / EM357 Address: 0x40004038 Reset: 0x0 ...

  • Page 54

    ... GPIO registers. Note: Because GPIO port registers’ functions are identical, the notation Px is used here to refer to PA, PB, or PC. For example, GPIO_PxIN refers to the registers GPIO_PAIN, GPIO_PBIN, and GPIO_PCIN. Figure 7-1. GPIO Block Diagram 7-1 Final EM351 / EM357 120-035X-000G ...

  • Page 55

    ... Push-pull output. GPIO_PxOUT controls the output. 0x5 Open-drain output. GPIO_PxOUT controls the output pull up is required, it must be external. 0x9 Push-pull output. An onboard peripheral controls the output. 0xD Open-drain output. An onboard peripheral controls the output pull up is required, it must be external. 7-2 Final EM351 / EM357 120-035X-000G ...

  • Page 56

    ... EM35x. Due to the fact that Serial Wire mode can only be invoked by an external debug tool Table 7-2. Timer 2 Output Configuration Controls Option Register Bit TIM2_OR[4] TIM2_OR[5] TIM2_OR[6] TIM2_OR[7] Table 7-3. GPIO Forced Functions 7-3 Final EM351 / EM357 GPIO Mapping Selected by TIM2_OR Bit 0 1 PA0 PB1 PA3 PB2 PA1 PB3 ...

  • Page 57

    ... Figure 7-2 shows the timing parameters for invoking serial bootload mode from a pin (nRESET) reset. Because OSCHF is running uncalibrated during the reset sequence, the time for 512 OSCHF clocks may vary as indicated. 7-4 Final EM351 / EM357 120-035X-000G ...

  • Page 58

    ... The internal pull-up and pull-down resistors are disabled. The Schmitt trigger input is connected to a high logic level. Reading GPIO_PxIN returns a constant 1. Figure 7-2. nBOOTMODE and nRESET Timing 26 µsec min. nRESET OSCHF nBOOTMODE 7-5 Final EM351 / EM357 . . . 512 clocks: 26 µsec min – 85 µsec max . . . . . . nBOOTMODE sampled 120-035X-000G ...

  • Page 59

    ... The internal pull-up and pull-down resistors are disabled. The Schmitt trigger input is connected to the pin. Reading GPIO_PxIN returns the input to the pin. Note: Depending on configuration and usage, GPIO_PxOUT and GPIO_PxIN may not have the same value. 7-6 Final EM351 / EM357 120-035X-000G ...

  • Page 60

    ... IRQC and IRQD, can use any GPIO pin. The GPIO_IRQCSEL and GPIO_IRQDSEL registers specify the GPIO pins assigned to IRQC and IRQD, respectively. Table 7-4 shows how the GPIO_IRQCSEL and GPIO_IRQDSEL register values select the GPIO pin used for the external interrupt. 7-7 Final EM351 / EM357 120-035X-000G ...

  • Page 61

    ... The GPIO signal assignments are shown in Table 7-5. Table 7-4. IRQC/D GPIO Selection GPIO GPIO_IRQxSEL PA0 8 PA1 9 PA2 10 PA3 11 PA4 12 PA5 13 PA6 14 PA7 15 7-8 Final EM351 / EM357 GPIO GPIO_IRQxSEL PB0 16 PB1 17 PB2 18 PB3 19 PB4 20 PB5 21 PB6 22 PB7 23 120-035X-000G GPIO PC0 PC1 ...

  • Page 62

    ... TIM2C3 , SC1SCLK, SC1nCTS 4 TIM2C4 , SC1nSSEL TIM2CLK, TIM1MSK TIM1C1, IRQB TIM1C2 5 JRST 5 JTDI 7 7 SWDIO , JTMS OSC32_EXT 7-9 Final EM351 / EM357 Output Current Drive Standard Standard Standard Standard Standard Standard High High Standard Standard Standard Standard Standard Standard High High High Standard ...

  • Page 63

    ... Alternate output, open-drain (peripheral controls the output). RW GPIO configuration control: see Px3_CFG above. RW GPIO configuration control: see Px3_CFG above. RW GPIO configuration control: see Px3_CFG above. 7-10 Final EM351 / EM357 Address: 0x4000B000 Reset: 0x4444 Address: 0x4000B400 Reset: 0x4444 Address: 0x4000B800 Reset: 0x4444 ...

  • Page 64

    ... Alternate output, open-drain (peripheral controls the output). RW GPIO configuration control: see Px7_CFG above. RW GPIO configuration control: see Px7_CFG above. RW GPIO configuration control: see Px7_CFG above. 7-11 Final EM351 / EM357 Address: 0x4000B004 Reset: 0x4444 Address: 0x4000B404 Reset: 0x4444 Address: 0x4000B804 Reset: 0x4444 ...

  • Page 65

    ... Input level at pin Px6. RW Input level at pin Px5. RW Input level at pin Px4. RW Input level at pin Px3. RW Input level at pin Px2. RW Input level at pin Px1. RW Input level at pin Px0. 7-12 Final EM351 / EM357 Address: 0x4000B008 Reset: 0x0 Address: 0x4000B408 Reset: 0x0 Address: 0x4000B808 Reset: 0x0 ...

  • Page 66

    ... Output data for Px6. RW Output data for Px5. RW Output data for Px4. RW Output data for Px3. RW Output data for Px2. RW Output data for Px1. RW Output data for Px0. 7-13 Final EM351 / EM357 Address: 0x4000B00C Reset: 0x0 Address: 0x4000B40C Reset: 0x0 Address: 0x4000B80C Reset: 0x0 ...

  • Page 67

    ... Write 1 to clear the output data bit for Px1 (writing 0 has no effect). W Write 1 to clear the output data bit for Px0 (writing 0 has no effect). 7-14 Final EM351 / EM357 Address: 0x4000B014 Reset: 0x0 Address: 0x4000B414 Reset: 0x0 Address: 0x4000B814 Reset: 0x0 26 25 ...

  • Page 68

    ... Write 1 to set the output data bit for Px1 (writing 0 has no effect). W Write 1 to set the output data bit for Px0 (writing 0 has no effect). 7-15 Final EM351 / EM357 Address: 0x4000B010 Reset: 0x0 Address: 0x4000B410 Reset: 0x0 Address: 0x4000B810 Reset: 0x0 26 25 ...

  • Page 69

    ... Write 1 to enable wakeup monitoring of Px4. RW Write 1 to enable wakeup monitoring of Px3. RW Write 1 to enable wakeup monitoring of Px2. RW Write 1 to enable wakeup monitoring of Px1. RW Write 1 to enable wakeup monitoring of Px0. 7-16 Final EM351 / EM357 Address: 0x4000BC08 Reset: 0x0 Address: 0x4000BC0C Reset: 0x0 Address: 0x4000BC10 Reset: 0x0 ...

  • Page 70

    ... IRQD_WAKE_FILTER Access Description RW Enable filter on GPIO wakeup source IRQD. RW Enable filter on GPIO wakeup source SC2 (PA2). RW Enable filter on GPIO wakeup source SC1 (PB2). RW Enable filter on GPIO wakeup sources enabled by the GPIO_PnWAKE registers. 7-17 Final EM351 / EM357 Address: 0x4000BC1C Reset: 0x0 ...

  • Page 71

    ... PB3. 0x0C: PB4. 0x0D: PB5. 0x0E: PB6. 0x0F: PB7. 0x10: PC0. 0x11: PC1. 0x12: PC2. 0x13: PC3. 0x14: PC4. 0x15: PC5. 0x16: PC6. 0x17: PC7. 0x18 - 0x1F: Reserved. 7-18 Final EM351 / EM357 Address: 0x4000BC14 Reset: 0xF Address: 0x4000BC18 Reset: 0x10 ...

  • Page 72

    ... Falling edge triggered. 0x3: Rising and falling edge triggered. 0x4: Active high level triggered. 0x5: Active low level triggered. 0x6, 0x7: Reserved. 7-19 Final EM351 / EM357 Address: 0x4000A860 Reset: 0x0 Address: 0x4000A864 Reset: 0x0 Address: 0x4000A868 Reset: 0x0 Address: 0x4000A86C Reset: 0x0 26 25 ...

  • Page 73

    ... IRQC interrupt pending. Write 1 to clear IRQC interrupt (writing 0 has no effect). RW IRQB interrupt pending. Write 1 to clear IRQB interrupt (writing 0 has no effect). RW IRQA interrupt pending. Write 1 to clear IRQA interrupt (writing 0 has no effect). 7-20 Final EM351 / EM357 Address: 0x4000A814 Reset: 0x0 ...

  • Page 74

    ... Disable debug interface ( not already active). RW Enable REG_EN override of PA7's normal GPIO configuration. 0: Disable override. 1: Enable override. RW Reserved: this bit can change during normal operation. When writing to GPIO_DBGCFG, the value of this bit must be preserved. 7-21 Final EM351 / EM357 Address: 0x4000BC00 Reset: 0x10 ...

  • Page 75

    ... R Status of debugger interface. 0: Debugger interface not forced active. 1: Debugger interface forced active by debugger cable. R Status of Serial Wire interface. 0: Not enabled by SWJ-DP. 1: Enabled by SWJ-DP. 7-22 Final EM351 / EM357 Address: 0x4000BC04 Reset: 0x0 ...

  • Page 76

    ... SCx_TWICTRL1 SCx_DATA SCx_TWICTRL2 TX-FIFO SCx_DMACTRL SCx_RXCNTA/B channel SCx_RXCNTSAVED DMA SCx_TX/RXBEGA/B Controller SCx_TX/RXENDA/B SCx_DMASTAT channel SCx_RXERRA/B RX-FIFO 8-1 Final EM351 / EM357 Baud Generator TXD RXD UART nRTS Controller nCTS SPI Slave MISO Controller MOSI SCLK SPI Master nSSEL Controller Clock Generator SCL ...

  • Page 77

    ... SC2MOSI SC2MISO Alternate Output Input (push-pull) SC2MOSI SC2MISO Input Alternate Output (push-pull) (not used) SC2SDA Alternate Output (open-drain) 8-2 Final EM351 / EM357 PB3 PB4 SC1SCLK (not used) Alternate Output (push-pull) SC1SCLK SC1nSSEL Input Input (not used) (not used) nCTS nRTS 1 Input ...

  • Page 78

    ... SC1_MODE Serial Mode Register SC2_MODE Serial Mode Register Bitname Bitfield SC_MODE [1: Access Description RW Serial controller mode. 0: Disabled. 1: UART mode (valid only for SC1). 2: SPI mode. 3: TWI mode. 8-3 Final EM351 / EM357 Address: 0x4000C854 Reset: 0x0 Address: 0x4000C054 Reset: 0x0 SC_MODE 120-035X-000G ...

  • Page 79

    ... Receive operation complete (TWI) interrupt pending. RW Transmit buffer underrun interrupt pending. RW Receive buffer overrun interrupt pending. RW Transmitter idle interrupt pending. RW Transmit buffer free interrupt pending. RW Receive buffer has data interrupt pending. 8-4 Final EM351 / EM357 Address: 0x4000A808 Reset: 0x0 Address: 0x4000A80C Reset: 0x0 ...

  • Page 80

    ... Receive operation complete (TWI) interrupt enable. RW Transmit buffer underrun interrupt enable. RW Receive buffer overrun interrupt enable. RW Transmitter idle interrupt enable. RW Transmit buffer free interrupt enable. RW Receive buffer has data interrupt enable. 8-5 Final EM351 / EM357 Address: 0x4000A848 Reset: 0x0 Address: 0x4000A84C Reset: 0x0 ...

  • Page 81

    ... Access Description RW Transmitter idle interrupt mode - 0: edge triggered, 1: level triggered. RW Transmit buffer free interrupt mode - 0: edge triggered, 1: level triggered. RW Receive buffer has data interrupt mode - 0: edge triggered, 1: level triggered. 8-6 Final EM351 / EM357 Address: 0x4000A854 Reset: 0x0 Address: 0x4000A858 Reset: 0x0 ...

  • Page 82

    ... Table 8-4). The bits SC_SPIPOL, SC_SPIPHA, and SC_SPIORD are defined within the SCx_SPICFG register. Table 8-3. SPI Master GPIO Usage MOSI MISO Output Input Input (push-pull) PB1 PB2 PA0 PA1 12 MHz + EXP 8-7 Final EM351 / EM357 SCLK Output Alternate Output (push-pull) PB3 PA2 120-035X-000G ...

  • Page 83

    ... To receive a character, you must transmit a character long stream of receive characters is expected, a long sequence of dummy transmit characters must be generated. To avoid software or transmit DMA initiating these transfers and consuming unnecessary bandwidth, the SPI serializer can be instructed to retransmit the Table 8-4. SPI Master Mode Formats Frame Formats 8-8 Final EM351 / EM357 120-035X-000G ...

  • Page 84

    ... Transmitted character while transmit FIFO was empty (transmit underrun error) To enable CPU interrupts, set the desired interrupt bits in the second-level INT_SCxCFG register, and enable the top-level SCx interrupt in the NVIC by writing the INT_SCx bit in the INT_CFGSET register. 8-9 Final EM351 / EM357 120-035X-000G ...

  • Page 85

    ... In UART mode (SC1 only), reading from this register loads the UART status register with the parity and frame error status of the next byte in the FIFO, and clears these bits if the FIFO is now empty. 8-10 Final EM351 / EM357 Address: 0x4000C83C Reset: 0x0 Address: 0x4000C03C Reset: 0x0 26 25 ...

  • Page 86

    ... Clock phase configuration: clear this bit to sample on the leading (first edge) and set this bit to sample on the second edge. RW Clock polarity configuration: clear this bit for a rising leading edge and set this bit for a falling leading edge. 8-11 Final EM351 / EM357 Address: 0x4000C858 Reset: 0x0 Address: 0x4000C058 Reset: 0x0 ...

  • Page 87

    ... This bit is set when the receive FIFO contains at least one byte. R This bit is set if a byte is received when the receive FIFO is full. This bit is cleared by reading the data register. 8-12 Final EM351 / EM357 Address: 0x4000C840 Reset: 0x0 Address: 0x4000C040 Reset: 0x0 ...

  • Page 88

    ... Serial Clock Linear Prescaler Register SC2_RATELIN Serial Clock Linear Prescaler Register Bitname Bitfield SC_RATELIN [3: Access Description RW The linear component (LIN) of the clock rate in the equation: rate = 12MHz / ( (LIN + 1) * (2^EXP) ) 8-13 Final EM351 / EM357 Address: 0x4000C860 Reset: 0x0 Address: 0x4000C060 Reset: 0x0 SC_RATELIN 120-035X-000G ...

  • Page 89

    ... SCLK (Serial Clock) – clocks data transfers on MOSI and MISO nSSEL (Slave Select) – enables serial communication with the slave Access Description RW The exponential component (EXP) of the clock rate in the equation: rate = 12MHz / ( (LIN + 1) * (2^EXP) ) 8-14 Final EM351 / EM357 Address: 0x4000C864 Reset: 0x0 Address: 0x4000C064 Reset: 0x0 SC_RATEEXP 120-035X-000G ...

  • Page 90

    ... The SPI slave controller receives its clock from an external SPI master device and supports rates Mbps. Table 8-5. SPI Slave GPIO Usage MISO SCLK Output Input Alternate Output Input (push-pull) PB1 PB3 PA1 PA2 8-15 Final EM351 / EM357 nSSEL Input Input PB4 PA3 120-035X-000G ...

  • Page 91

    ... FIFO is full are dropped, and the SC_SPIRXOVF bit in the SCx_SPISTAT register is set. The receive FIFO hardware generates the INT_SCRXOVF interrupt, but the DMA register will not indicate the error Table 8-6. SPI Slave Formats 8-16 Final EM351 / EM357 120-035X-000G ...

  • Page 92

    ... Transmitted character while transmit FIFO was empty (transmit underrun error) To enable CPU interrupts, set desired interrupt bits in the second-level INT_SCxCFG register, and also enable the top-level SCx interrupt in the NVIC by writing the INT_SCx bit in the INT_CFGSET register. 8-17 Final EM351 / EM357 120-035X-000G ...

  • Page 93

    ... MHz according to this equation: 2 C-bus slave devices Table 8-7. TWI Master GPIO Usage SDA Input / Output Alternate Output (open drain) PB1 PA1 12 MHz = rate + EXP ( LIN 8-18 Final EM351 / EM357 SCL Input / Output Alternate Output (open drain) PB2 PA2 120-035X-000G ...

  • Page 94

    ... This inhibits further data transfers until SCL is allowed to go high again. 8.5.3 Constructing Frames The TWI master controller supports generating various frame segments by means of the SC_TWISTART, SC_TWISTOP, SC_TWISEND, and SC_TWIRECV bits in the SCx_TWICTRL1 registers. Table 8-9 summarizes these frames. SCx_RATELIN 8-19 Final EM351 / EM357 SCx_RATEEXP 120-035X-000G ...

  • Page 95

    ... Table 8-9. TWI Master Frame Segments SCx_TWICTRL1 1 SC_TWIxxxx Frame Segments START SEND RECV STOP pending frame segment Illegal - The notation xxx means that the corresponding column header below is inserted to form the field name. 8-20 Final EM351 / EM357 120-035X-000G ...

  • Page 96

    ... Interrupts TWI master controller interrupts are generated on the following events: Bus command (SC_TWISTART/SC_TWISTOP) completed ( transition of SC_TWICMDFIN) Character transmitted and slave device responded with NACK IDLE START Segment TRANSMIT Segment NO received ACK ? YES RECEIVE Segment with ACK 8-21 Final EM351 / EM357 120-035X-000G ...

  • Page 97

    ... This bit is set when a byte is received. It clears on the next TWI bus activity. R This bit is set when a byte is transmitted. It clears on the next TWI bus activity. R This bit is set when a NACK is received from the slave. It clears on the next TWI bus activity. 8-22 Final EM351 / EM357 Address: 0x4000C844 Reset: 0x0 Address: 0x4000C044 Reset: 0x0 ...

  • Page 98

    ... Setting this bit sends the START or repeated START command. It clears when the command completes. RW Setting this bit transmits a byte. It clears when the command completes. RW Setting this bit receives a byte. It clears when the command completes. 8-23 Final EM351 / EM357 Address: 0x4000C84C Reset: 0x0 Address: 0x4000C04C Reset: 0x0 ...

  • Page 99

    ... To Send) – inhibits sending data from the EM35x if not asserted Access Description RW Setting this bit signals ACK after a received byte. Clearing this bit signals NACK after a received byte. 8-24 Final EM351 / EM357 Address: 0x4000C850 Reset: 0x0 Address: 0x4000C050 Reset: 0x0 SC_TWIACK 120-035X-000G ...

  • Page 100

    ... Table 8-10. UART GPIO Usage RXD Input Input PB2 24 MHz + SC1_UARTFRAC 40000 0 5000 0 2500 0 1250 0 625 0 312 1 208 1 104 8-25 Final EM351 / EM357 1 1 nCTS nRTS Input Output Input Alternate Output (push-pull) PB3 PB4 Baud Rate Error (%) 0.08 + 0.16 + 0.16 + 0.16 + 0.16 120-035X-000G ...

  • Page 101

    ... Note that asynchronous serial data may have arbitrarily long idle periods between characters. When idle, serial data (TXD or RXD) is held in the high state. Serial data transitions to the low state in the start bit at the beginning of a character frame. 8-26 Final EM351 / EM357 120-035X-000G ...

  • Page 102

    ... UART Character Frame Format (optional sections are in italics) Data Data Data Data Data Data Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 8-4. UART FIFOs 8-27 Final EM351 / EM357 Next Parity Stop Stop Start Bit Bit Bit Bit or IdleTime 120-035X-000G ...

  • Page 103

    ... SCx interrupt in the NVIC by writing the INT_SCx bit in the INT_CFGSET register. Operating Mode No RTS/CTS flow control Flow control using RTS/CTS with software control of nRTS: nRTS controlled by SC_UARTRTS bit in SC1_UARTCFG register Flow control using RTS/CTS with hardware control of nRTS: nRTS is asserted if room for at least 2 characters in receive FIFO 8-28 Final EM351 / EM357 120-035X-000G ...

  • Page 104

    ... This bit shows the logical state (not voltage level) of the nCTS input: 0: nCTS is deasserted (pin is high, 'XOFF', RS232 negative voltage); the UART is inhibited from starting to transmit a byte. 1: nCTS is asserted (pin is low, 'XON', RS232 positive voltage); the UART may transmit. 8-29 Final EM351 / EM357 Address: 0x4000C848 Reset: 0x40 ...

  • Page 105

    ... SC_UARTAUTO must be cleared). When this bit is set, nRTS is asserted (pin is low, 'XON', RS232 positive voltage); the other device's transmission is enabled. When this bit is cleared, nRTS is deasserted (pin is high, 'XOFF', RS232 negative voltage), the other device's transmission is inhibited. 8-30 Final EM351 / EM357 Address: 0x4000C85C Reset: 0x0 ...

  • Page 106

    ... SC1_UARTPER UART Baud Rate Period Register Bitname Bitfield SC_UARTPER [15: SC_UARTPER SC_UARTPER Access Description RW The integer part of baud rate period (N) in the equation: rate = 24MHz / ( ( 8-31 Final EM351 / EM357 Address: 0x4000C868 Reset: 0x0 120-035X-000G ...

  • Page 107

    ... Enable top-level NVIC interrupts by setting the INT_SCx bit in the INT_CFGSET register. Start the DMA by loading the DMA buffers by setting the SC_TXLODA/B (or SC_RXLODA/B) bits in the SCx_DMACTRL register Access Description RW The fractional part of the baud rate period (F) in the equation: rate = 24MHz / ( ( 8-32 Final EM351 / EM357 Address: 0x4000C86C Reset: 0x0 SC_UARTFRAC 120-035X-000G ...

  • Page 108

    ... Serial controller DMA channels include additional features specific to the SPI and UART operation and are described in those sections. 8-33 Final EM351 / EM357 120-035X-000G ...

  • Page 109

    ... A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has no effect. Reading this bit returns DMA buffer status: 0: DMA processing is complete or idle. 1: DMA processing is active or pending. 8-34 Final EM351 / EM357 Address: 0x4000C830 Reset: 0x0 Address: 0x4000C030 Reset: 0x0 ...

  • Page 110

    ... This bit is set when DMA transmit buffer B is active. R This bit is set when DMA transmit buffer A is active. R This bit is set when DMA receive buffer B is active. R This bit is set when DMA receive buffer A is active. 8-35 Final EM351 / EM357 Address: 0x4000C82C Reset: 0x0 Address: 0x4000C02C Reset: 0x0 ...

  • Page 111

    ... SCx_TXBEGA SC1_TXBEGA Transmit DMA Begin Address Register A SC2_TXBEGA Transmit DMA Begin Address Register Bitname Bitfield SC_TXBEGA [13: SC_TXBEGA Access Description RW DMA transmit buffer A start address. 8-36 Final EM351 / EM357 Address: 0x4000C810 Reset: 0x20000000 Address: 0x4000C010 Reset: 0x20000000 SC_TXBEGA 120-035X-000G ...

  • Page 112

    ... SCx_TXBEGB SC1_TXBEGB Transmit DMA Begin Address Register B SC2_TXBEGB Transmit DMA Begin Address Register Bitname Bitfield SC_TXBEGB [13: SC_TXBEGB Access Description RW DMA transmit buffer B start address. 8-37 Final EM351 / EM357 Address: 0x4000C818 Reset: 0x20000000 Address: 0x4000C018 Reset: 0x20000000 SC_TXBEGB 120-035X-000G ...

  • Page 113

    ... Transmit DMA End Address Register A SC2_TXENDA Transmit DMA End Address Register Bitname Bitfield SC_TXENDA [13: SC_TXENDA Access Description RW Address of the last byte that will be read from the DMA transmit buffer A. 8-38 Final EM351 / EM357 Address: 0x4000C814 Reset: 0x20000000 Address: 0x4000C014 Reset: 0x20000000 SC_TXENDA 120-035X-000G ...

  • Page 114

    ... Transmit DMA End Address Register B SC2_TXENDB Transmit DMA End Address Register Bitname Bitfield SC_TXENDB [13: SC_TXENDB Access Description RW Address of the last byte that will be read from the DMA transmit buffer B. 8-39 Final EM351 / EM357 Address: 0x4000C81C Reset: 0x20000000 Address: 0x4000C01C Reset: 0x20000000 SC_TXENDB 120-035X-000G ...

  • Page 115

    ... The offset from the start of the active DMA transmit buffer from which the next byte will be read. This register is set to zero when the buffer is loaded and when the DMA is reset. 8-40 Final EM351 / EM357 Address: 0x4000C828 Reset: 0x0 Address: 0x4000C028 Reset: 0x0 26 ...

  • Page 116

    ... SCx_RXBEGA SC1_RXBEGA Receive DMA Begin Address Register A SC2_RXBEGA Receive DMA Begin Address Register Bitname Bitfield SC_RXBEGA [13: SC_RXBEGA Access Description RW DMA receive buffer A start address. 8-41 Final EM351 / EM357 Address: 0x4000C800 Reset: 0x20000000 Address: 0x4000C000 Reset: 0x20000000 SC_RXBEGA 120-035X-000G ...

  • Page 117

    ... SCx_RXBEGB SC1_RXBEGB Receive DMA Begin Address Register B SC2_RXBEGB Receive DMA Begin Address Register Bitname Bitfield SC_RXBEGB [13: SC_RXBEGB Access Description RW DMA receive buffer B start address. 8-42 Final EM351 / EM357 Address: 0x4000C808 Reset: 0x20000000 Address: 0x4000C008 Reset: 0x20000000 SC_RXBEGB 120-035X-000G ...

  • Page 118

    ... Receive DMA End Address Register A SC2_RXENDA Receive DMA End Address Register Address: 0x4000C004 Reset: 0x20000000 Bitname Bitfield SC_RXENDA [13: SC_RXENDA Access Description RW Address of the last byte that will be written in the DMA receive buffer A. 8-43 Final EM351 / EM357 Address: 0x4000C804 Reset: 0x20000000 SC_RXENDA 120-035X-000G ...

  • Page 119

    ... Receive DMA End Address Register B SC2_RXENDB Receive DMA End Address Register Bitname Bitfield SC_RXENDB [13: SC_RXENDB Access Description RW Address of the last byte that will be written in the DMA receive buffer B. 8-44 Final EM351 / EM357 Address: 0x4000C80C Reset: 0x20000000 Address: 0x4000C00C Reset: 0x20000000 SC_RXENDB 120-035X-000G ...

  • Page 120

    ... The offset from the start of DMA receive buffer A at which the next byte will be written. This register is set to zero when the buffer is loaded and when the DMA is reset. If this register is written when the buffer is not loaded, the buffer is loaded. 8-45 Final EM351 / EM357 Address: 0x4000C820 Reset: 0x0 Address: 0x4000C020 Reset: 0x0 26 25 ...

  • Page 121

    ... The offset from the start of DMA receive buffer B at which the next byte will be written. This register is set to zero when the buffer is loaded and when the DMA is reset. If this register is written when the buffer is not loaded, the buffer is loaded. 8-46 Final EM351 / EM357 Address: 0x4000C824 Reset: 0x0 Address: 0x4000C024 Reset: 0x0 26 25 ...

  • Page 122

    ... Saved Receive DMA Count Register Bitname Bitfield SC_RXCNTSAVED [13: SC_RXCNTSAVED SC_RXCNTSAVED Access Description R Receive DMA count saved in SPI slave mode when nSSEL deasserts. The count is only saved the first time nSSEL deasserts. 8-47 Final EM351 / EM357 Address: 0x4000C870 Reset: 0x0 Address: 0x4000C070 Reset: 0x0 120-035X-000G ...

  • Page 123

    ... FIFO, so this offset is 4 bytes before the overflow position. If there is no error, it reads zero. This register will not be updated by subsequent errors until the buffer unloads and is reloaded, or the receive DMA is reset. 8-48 Final EM351 / EM357 Address: 0x4000C834 Reset: 0x0 Address: 0x4000C034 Reset: 0x0 26 25 ...

  • Page 124

    ... FIFO, so this offset is 4 bytes before the overflow position. If there is no error, it reads zero. This register will not be updated by subsequent errors until the buffer unloads and is reloaded, or the receive DMA is reset. 8-49 Final EM351 / EM357 Address: 0x4000C838 Reset: 0x0 Address: 0x4000C038 Reset: 0x0 26 25 ...

  • Page 125

    General Purpose Timers (TIM1 and TIM2) 9.1 Introduction Each of the EM35x’s two general-purpose timers consists of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse ...

  • Page 126

    Figure 9-1. General-Purpose Timer Block Diagram Note: The internal signals shown in Figure 9-1 are described in the Timer Signal Descriptions section, and are used throughout the text to describe how the timer components are interconnected. 9-2 Final 120-035X-000G ...

  • Page 127

    ... Table 9-1. Timer GPIO Usage TIMxC1 TIMxC2 TIMxC3 (in or out) (in or out) (in or out) PB6 PB7 PA6 PA0 PA3 PA1 PB1 PB2 PB3 9-3 Final EM351 / EM357 TIMxC4 TIMxCLK TIMxMSK (in or out) (in) (in) PA7 PB0 PB5 PA2 PB5 PB0 PB4 PB5 PB0 120-035X-000G ...

  • Page 128

    TIMx_CR1 register. The UEV is generated when both the counter reaches the overflow (or underflow when down-counting) and when the TIM_UDIS bit equals 0 in the TIMx_CR1 ...

  • Page 129

    INT_TIMUIF flag. Thus no interrupt request is sent. This avoids generating both update and capture interrupts when clearing the counter on the capture event. When a UEV occurs, the update flag (the INT_TIMUIF bit in the ...

  • Page 130

    Figure 9-5. Counter Timing Diagram, Update Event when TIM_ARBE = 0 (TIMx_ARR not buffered) Figure 9-6. Counter Timing Diagram, Update Event when TIM_ARBE = 1 (TIMx_ARR buffered) Down-Counting Mode 9.3.2.2 In down-counting mode, the counter counts from the auto-reload value ...

  • Page 131

    When a UEV occurs, the update flag (the INT_TIMUIF bit in the INT_TIMxFLAG register) is set (unless TIM_USR is 1) and the following registers are updated: The prescaler shadow register is reloaded with the buffer value (contents of the TIMx_PSC ...

  • Page 132

    In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit generates a UEV, but without setting the INT_TIMUIF flag. Thus no interrupt request is sent. This avoids generating both update and capture interrupt when ...

  • Page 133

    Figure 9-11. Counter Timing Diagram, Update Event with TIM_ARBE = 1 (counter overflow) 9.3.3 Clock Selection The counter clock can be provided by the following clock sources: Internal clock (PCLK) External clock mode 1: external input pin (TIy) External clock ...

  • Page 134

    Figure 9-13. TI2 External Clock Connection Example For example, to configure the up-counter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input: ...

  • Page 135

    ... The counter counts once each 2 ETR rising edges. The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Figure 9-16 illustrates counting every 2 rising edges of ETR using external clock mode 2. 9-11 Final EM351 / EM357 120-035X-000G ...

  • Page 136

    Figure 9-16. Control Circuit in External Clock Mode 2 9.3.4 Capture/Compare Channels Each capture/compare channel is built around a capture/compare register including a shadow register, an input stage for capture with digital filter, multiplexing and prescaler, and an output stage ...

  • Page 137

    Figure 9-18. Capture/Compare Channel 1 Main Circuit Figure 9-19 show details of the output stage of a capture/compare channel. Figure 9-19. Output Stage of Capture/Compare Channel (Channel 1) The capture/compare block is made of a buffer register and a shadow ...

  • Page 138

    If a capture occurs when the INT_TIMCCyIF flag is already high, then the missed capture flag INT_TIMMISSCCyIF in the INT_TIMxMISS register is set. INT_TIMCCyIF can be cleared by software writing its bit or reading the captured data ...

  • Page 139

    Select the active input for TIMx_CCR2by writing the TIM_CC2S bits the TIMx_CCMR1 register (TI1 selected). Select the active polarity for TI1FP2 (used for capture in the TIMx_CCR2) by writing the TIM_CC2P bit to 1 (active on falling ...

  • Page 140

    Sets a flag in the interrupt flag register (the INT_TIMCCyIF bit in the INT_TIMxFLAG register). Generates an interrupt if the corresponding interrupt mask is set (the TIM_CCyIF bit in the INT_TIMxCFG register). The TIMx_CCRy registers can be programmed with or ...

  • Page 141

    Because the buffer registers are only transferred to the shadow registers when a UEV occurs, before starting the counter initialize all the registers by setting the TIM_UG bit in the TIMx_EGR register. OCy polarity is software programmable using the TIM_CCyP ...

  • Page 142

    PWM Center-Aligned Mode 9.3.9.3 Center-aligned mode is active except when the TIM_CMS bits in the TIMx_CR1 register are 00 (all configurations where TIM_CMS is non-zero have the same effect on the OCyREF/OCy signals). The compare flag is set when the ...

  • Page 143

    Hints on using center-aligned mode: When starting in center-aligned mode, the current up-down configuration is used. This means that the counter counts up or down depending on the value written in the TIM_DIR bit in the TIMx_CR1 register. The TIM_DIR ...

  • Page 144

    Figure 9-24 illustrates this example. Figure 9-24. Example of One Pulse Mode 9.3.10.1 A Special Case: OCy Fast Enable In one-pulse mode, the edge detection on the TIy input sets the TIM_CEN bit, which enables the counter. Then the comparison ...

  • Page 145

    ... TIM_CEN = 1 (TIMx_CR1 register, counter is enabled). Figure 9-25. Example of Counter Operation in Encoder Interface Mode TI1FP1 Signal Rising Falling Down Up Up Down No Count No Count No Count No Count Down Up Up Down 9-21 Final EM351 / EM357 TI2FP2 Signal Rising Falling No Count No Count No Count No Count Up Down Down Up Up Down Down Up 120-035X-000G ...

  • Page 146

    Figure 9-26 gives an example of counter behavior when IC1FP1 polarity is inverted (same configuration as above except TIM_CC1P = 1). Figure 9-26. Example of Encoder Interface Mode with IC1FP1 Polarity Inverted The timer configured in encoder interface mode provides ...

  • Page 147

    The counter starts counting on the internal clock, then behaves normally until the TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (the INT_TIMTIF bit in the ...

  • Page 148

    Slave Mode: Trigger Mode 9.3.13.3 In trigger mode the counter starts in response to an event on a selected input. In the following example, the up-counter starts in response to a rising edge on the TI2 input: Configure channel 2 ...

  • Page 149

    A rising edge on TI1 enables the counter and sets the INT_TIMTIF flag. The counter then counts on ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due ...

  • Page 150

    Using One Timer to Enable the Other Timer 9.3.14.2 In this example, shown in Figure 9-32, the enable of Timer 2 is controlled with the output compare 1 of Timer 1. Timer 2 counts on the divided internal clock only ...

  • Page 151

    Figure 9-33. Gating Timer 2 with Enable of Timer 1 9.3.14.3 Using One Timer to Start the Other Timer In this example (see Figure 9-34), the enable of Timer 2 is set with the UEV of Timer 1. Timer 2 ...

  • Page 152

    Figure 9-35. Triggering Timer 2 with Enable of Timer 1 Starting both Timers Synchronously in Response to an External Trigger 9.3.14.4 This example sets the enable of Timer 1 when its TI1 input rises, and the enable of Timer 2 ...

  • Page 153

    ... Timer channel at a GPIO pin: can be a capture input (ICy compare output (OCy). TIMxCLK External Clock input (if selected) to the external trigger signal (ETR). TIMxMSK External Clock mask (if enabled) AND’ed with the other timer’s TIMxCLK signal. TRGI Internal Trigger input for slave mode controller. 9-29 Final EM351 / EM357 120-035X-000G ...

  • Page 154

    Interrupts Each timer has its own top-level NVIC interrupt. Writing 1 to the INT_TIMx bit in the INT_CFGSET register enables the TIMx interrupt, and writing 1 to the INT_TIMx bit in the INT_CFGCLR register disables it. Chapter 11, Interrupt ...

  • Page 155

    Registers TIMx_CR1 TIM1_CR1 Timer 1 Control Register 1 TIM2_CR1 Timer 2 Control Register TIM_ARBE TIM_CMS Bitname Bitfield TIM_ARBE [7] TIM_CMS [6:5] TIM_DIR [4] TIM_OPM ...

  • Page 156

    Bitname Bitfield TIM_CEN [0] Access Description RW Counter Enable. 0: Counter disabled. 1: Counter enabled. Note: External clock, gated mode and encoder mode can work only if the TIM_CEN bit has been previously set by software. Trigger mode sets the ...

  • Page 157

    TIMx_CR2 TIM1_CR2 Timer 1 Control Register 2 TIM2_CR2 Timer 2 Control Register TIM_TI1S Bitname Bitfield TIM_TI1S [7] TIM_MMS [6: ...

  • Page 158

    TIMx_SMCR TIM1_SMCR Timer 1 Slave Mode Control Register TIM2_SMCR Timer 2 Slave Mode Control Register TIM_ETP TIM_ECE 7 6 TIM_MSM Bitname Bitfield TIM_ETP [15] TIM_ECE [14] TIM_ETPS [13:12 ...

  • Page 159

    Bitname Bitfield TIM_ETF [11:8] TIM_MSM [7] TIM_TS [6:4] TIM_SMS [2:0] Access Description RW External Trigger Filter. This defines the frequency used to sample the ETRP signal, Fsampling, and the length of the digital filter applied to ETRP. The digital filter ...

  • Page 160

    TIMx_EGR TIM1_EGR Timer 1 Event Generation Register TIM2_EGR Timer 2 Event Generation Register TIM_TG Bitname Bitfield TIM_TG [6] TIM_CC4G [4] TIM_CC3G [3] TIM_CC2G [2] TIM_CC1G ...

  • Page 161

    TIM1_CCMR1 TIM1_CCMR1 Timer 1 Capture/Compare Mode Register 1 TIM2_CCMR1 Timer 2 Capture/Compare Mode Register TIM_IC2F TIM_IC1F Timer channels can be programmed as inputs (capture mode) ...

  • Page 162

    Bitname Bitfield TIM_OC2FE [10] TIM_IC2F [15:12] TIM_IC2PSC [11:10] TIM_CC2S [9:8] TIM_OC1M [6:4] TIM_OC1BE [3 TIM_OC1FE [2] TIM_IC1F [7:4] TIM_IC1PSC [3:2] Access Description RW Output Compare 2 Fast Enable. (Applies only if TIM_CC2S = 0.) This bit speeds the effect of ...

  • Page 163

    Bitname Bitfield TIM_CC1S [1:0] Access Description RW Capture / Compare 1 Selection. This configures the channel as an output or an input input, it selects the input source. 00: Channel is an output. 01: Channel is an input ...

  • Page 164

    TIMx_CCMR2 TIM1_CCMR2 Timer 1 Capture/Compare Mode Register 2 TIM2_CCMR2 Timer 2 Capture/Compare Mode Register TIM_IC4F TIM_IC3F Timer channels can be programmed as inputs (capture mode) ...

  • Page 165

    Bitname Bitfield TIM_OC4FE [10] TIM_IC4F [15:12] TIM_IC4PSC [11:10] TIM_CC4S [9:8] TIM_OC3M [6:4] TIM_OC3BE [3 TIM_OC3FE [2] TIM_IC3F [7:4] TIM_IC3PSC [3:2] Access Description RW Output Compare 4 Fast Enable. (Applies only if TIM_CC4S = 0.) This bit speeds the effect of ...

  • Page 166

    Bitname Bitfield TIM_CC3S [1:0] Access Description RW Capture / Compare 3 Selection. This configures the channel as an output or an input input, it selects the input source. 00: Channel is an output. 01: Channel is an input ...

  • Page 167

    TIMx_CCER TIM1_CCER Timer 1 Capture/Compare Enable Register TIM2_CCER Timer 2 Capture/Compare Enable Register Bitname Bitfield TIM_CC4P [13] TIM_CC4E [12] TIM_CC3P [9] TIM_CC3E [8] TIM_CC2P ...

  • Page 168

    TIMx_CNT TIM1_CNT Timer 1 Counter Register TIM2_CNT Timer 2 Counter Register Bitname Bitfield TIM_CNT [15: ...

  • Page 169

    TIMx_PSC TIM1_PSC Timer 1 Prescaler Register TIM2_PSC Timer 2 Prescaler Register Bitname Bitfield TIM_PSC [3: ...

  • Page 170

    TIMx_ARR TIM1_ARR Timer 1 Auto-Reload Register TIM2_ARR Timer 2 Auto-Reload Register Bitname Bitfield TIM_ARR [15: ...

  • Page 171

    TIMx_CCR1 TIM1_CCR1 Timer 1 Capture/Compare Register 1 TIM2_CCR1 Timer 2 Capture/Compare Register Bitname Bitfield TIM_CCR [15: ...

  • Page 172

    TIMx_CCR2 TIM1_CCR2 Timer 1 Capture/Compare Register 2 TIM2_CCR2 Timer 2 Capture/Compare Register Bitname Bitfield TIM_CCR [15: ...

  • Page 173

    TIMx_CCR3 TIM1_CCR3 Timer 1 Capture/Compare Register 3 TIM2_CCR3 Timer 2 Capture/Compare Register Bitname Bitfield TIM_CCR [15: ...

  • Page 174

    TIMx_CCR4 TIM1_CCR4 Timer 1 Capture/Compare Register 4 TIM2_CCR4 Timer 2 Capture/Compare Register Bitname Bitfield TIM_CCR [15: ...

  • Page 175

    TIM1_OR Timer 1 Option Register Bitname Bitfield TIM_ORRSVD [3] TIM_CLKMSKEN [2] TIM1_EXTRIGSEL [1: ...

  • Page 176

    TIM2_OR Timer 2 Option Register TIM_REMAPC4 TIM_REMAPC3 Bitname Bitfield TIM_REMAPC4 [7] TIM_REMAPC3 [6] TIM_REMAPC2 [5] TIM_REMAPC1 [4] TIM_ORRSVD [3] TIM_CLKMSKEN [2] TIM1_EXTRIGSEL [1: ...

  • Page 177

    INT_TIMxCFG INT_TIM1CFG Timer 1 Interrupt Configuration Register INT_TIM2CFG Timer 2 Interrupt Configuration Register INT_TIMTIF Bitname Bitfield INT_TIMTIF [6] INT_TIMCC4IF [4] INT_TIMCC3IF [3] INT_TIMCC2IF [2] INT_TIMCC1IF ...

  • Page 178

    INT_TIMxFLAG INT_TIM1FLAG Timer 1 Interrupt Flag Register INT_TIM2FLAG Timer 2 Interrupt Flag Register INT_TIMTIF Bitname Bitfield INT_TIMRSVD [12:9] INT_TIMTIF [6] INT_TIMCC4IF [4] INT_TIMCC3IF [3] INT_TIMCC2IF ...

  • Page 179

    INT_TIMxMISS INT_TIM1MISS Timer 1 Missed Interrupt Register INT_TIM2MISS Timer 2 Missed Interrupts Register Bitname Bitfield INT_TIMMISSCC4IF [12] INT_TIMMISSCC3IF [11] INT_TIMMISSCC2IF [10] INT_TIMMISSCC1IF [9] INT_TIMMISSRSVD [6:0] ...

  • Page 180

    ... Configure any GPIO pins to be used by the ADC in analog mode. Configure the voltage reference (internal or external). Set the offset and gain values. If using DMA, reset the ADC DMA, define the DMA buffer, and start the DMA in the proper transfer mode. Figure 10-1. ADC Block Diagram 10-1 Final EM351 / EM357 120-035X-000G ...

  • Page 181

    ... Although ADC_GAIN can represent a much greater range, its purpose is to correct small gain error, and in practice is loaded with values within a range of about 0.95 to 1.05. Table 10-1. ADC GPIO Pin Usage GPIO Configuration control PB5 GPIO_PBCFGH[7:4] PB6 GPIO_PBCFGH[11:8] PB7 GPIO_PBCFGH[15:12] PC1 GPIO_PCCFGL[7:4] PA4 GPIO_PACFGH[3:0] PA5 GPIO_PACFGH[7:4] PB0 GPIO_PBCFGL[3:0] 10-2 Final EM351 / EM357 120-035X-000G ...

  • Page 182

    ... The ADC configuration register (ADC_CFG) sets up most of the ADC operating parameters. 10.1.5.1 Input The analog input of the ADC can be chosen from various sources. The analog input is configured with the ADC_MUXP and ADC_MUXN bits within the ADC_CFG register. Table 10-2 shows the possible input selections. 10-3 Final EM351 / EM357 120-035X-000G ...

  • Page 183

    ... PB5 PB6 PB7 PC1 PA4 PA5 Internal connection Calibration Internal connection Calibration Internal connection Calibration Internal connection Supply monitoring and calibration ADC_MUXP ADC_MUXN 10-4 Final EM351 / EM357 Purpose 9 Single-ended 9 Single-ended 9 Single-ended 9 Single-ended 9 Single-ended 9 Single-ended 0 Differential 2 Differential 4 Differential 9 Calibration 9 Calibration 9 Calibration 120-035X-000G ...

  • Page 184

    ... Final EM351 / EM357 Sample Frequency (kHz) Significant Bits 1 MHz clock 6 MHz clock 31.3 188 15.6 93.8 7.81 46.9 3.91 23.4 1.95 11.7 0.977 5.86 0.488 2 ...

  • Page 185

    ... GPIOs and the voltage reference have already been configured. 1. Allocate a 16-bit signed variable, for example analogData, to receive the ADC output. (Make sure that analogData is half-word aligned – that is even address.) 2. Disable all ADC interrupts: Write 0 to the INT_ADCCFG register. 10-6 Final EM351 / EM357 120-035X-000G ...

  • Page 186

    ... GND two’s complement value 32768 as the conversion result. Instead, VGND yields a value close to 57344 when Table 10-5. ADC Gain and offset correction equations Correction value × 32768 ( N × 57344 10-7 Final EM351 / EM357 16384 − VREF GND − GND 120-035X-000G ...

  • Page 187

    ... Final EM351 / EM357 = 7. dBFS level (where full-scale is a Nyquist = 7. dBFS level (where full- input Nyquist Performance 256 512 1024 2048 1.95k 977 488 244 1 ...

  • Page 188

    ... Nyquist = 7.7% f input Nyquist Performance 10.7 21.3 42.7 46.9k 23.4k 11.7k 28.3k 14.1k 7.07k 0.084 0.15 0.274 0.044 0.076 0.147 10-9 Final EM351 / EM357 -69 -69 -69 -69 -75 -76 -76 -76 11.3 12.2 12 ...

  • Page 189

    ... Nyquist = 7. level = 1.2 V p-p swing and a input Nyquist Performance 128 256 46.9k 23.4k 11.7k 10-10 Final EM351 / EM357 0.096 0.119 0.196 0.371 0.024 0.03 0.05 0.082 11.4 12.6 13.1 13 ...

  • Page 190

    ... Table 10-9. ADC Specifications Min. Typ. 1.17 1.2 10-11 Final EM351 / EM357 1.77k 884 442 0.261 0.522 1.028 0.167 0.326 0.65 0.167 0.326 0.65 0.013 0.023 0.038 9.5 10.7 11.3 11.6 59 ...

  • Page 191

    ... Min. Typ. 1.1 1 -VREF 0 -10 1 0.5 10 10-12 Final EM351 / EM357 Max. Units 1.3 V MΩ V VREF V VREF V +VREF V ...

  • Page 192

    ... ADC Data Register Bitname Bitfield ADC_DATA_FIELD [15: ADC_DATA_FIELD ADC_DATA_FIELD Access Description R ADC conversion result. The result is a signed 2’s complement value. The significant bits of the value begin at bit 15 regardless of the sample period used. 10-13 Final EM351 / EM357 Address: 0x4000D000 Reset: 0x00000000 120-035X-000G ...

  • Page 193

    ... Enable the ADC: write 1 to enable continuous conversions, write 0 to stop. When the ADC is started the first conversion takes twice the usual number of clocks plus 21 microseconds. If anything in this register is modified while the ADC is running, the next conversion takes twice the usual number of clocks. 10-14 Final EM351 / EM357 Address: 0x4000D004 Reset: 0x00001800 ...

  • Page 194

    ... ADC_OFFSET ADC Offset Register Bitname Bitfield ADC_OFFSET_FIELD [15: ADC_OFFSET_FIELD ADC_OFFSET_FIELD Access Description RW 16-bit signed offset added to the basic ADC conversion result before gain correction is applied. 10-15 Final EM351 / EM357 Address: 0x4000D008 Reset: 0x0000 120-035X-000G ...

  • Page 195

    ... Gain factor that is multiplied by the offset-corrected ADC result to produce the output value. The gain is a 16-bit unsigned scaled integer value with a binary decimal point between bits 15 and 14. It can represent values from 0 to (almost) 2. The reset value is a gain factor of 1. 10-16 Final EM351 / EM357 Address: 0x4000D00C Reset: 0x8000 ...

  • Page 196

    ... Linear mode, the DMA stops when the buffer is full. 1: Auto-wrap mode, the DMA output wraps back to the start when the buffer is full. RW Loads the DMA buffer. Write 1 to start DMA (writing 0 has no effect). Cleared when DMA starts or is reset. 10-17 Final EM351 / EM357 Address: 0x4000D010 Reset: 0x0 ...

  • Page 197

    ... ADC DMA Status Register Bitname Bitfield ADC_DMAOVF [1] ADC_DMAACT [ Access Description R DMA overflow: occurs when an ADC result is ready and the DMA is not active. Cleared by DMA reset. R DMA status: reads 1 if DMA is active. 10-18 Final EM351 / EM357 Address: 0x4000D014 Reset: 0x0 ADC_DMAOVF ADC_DMAACT 120-035X-000G ...

  • Page 198

    ... ADC_DMABEG ADC DMA Begin Address Register Bitname Bitfield ADC_DMABEG [13: ADC_DMABEG Access Description RW ADC buffer start address. Caution: this must be an even address - the least significant bit of this register is fixed at zero by hardware. 10-19 Final EM351 / EM357 Address: 0x4000D018 Reset: 0x20000000 ADC_DMABEG 120-035X-000G ...

  • Page 199

    ... Bitname Bitfield ADC_DMASIZE_FIELD [12: ADC_DMASIZE_FIELD Access Description RW ADC buffer size. This is the number of 16-bit ADC conversion results the buffer can hold, not its length in bytes. (The length in bytes is twice this value.) 10-20 Final EM351 / EM357 Address: 0x4000D01C Reset: 0x0 ADC_DMASIZE_FIELD 2 1 120-035X-000G ...

  • Page 200

    ... ADC_DMACUR ADC DMA Current Address Register Bitname Bitfield ADC_DMACUR_FIELD [13: ADC_DMACUR_FIELD ADC_DMACUR_FIELD Access Description R Current DMA address: the location that will be written next by the DMA. 10-21 Final EM351 / EM357 Address: 0x4000D020 Reset: 0x20000000 120-035X-000G ...