EM357-RTR Ember, EM357-RTR Datasheet - Page 110

• Manufacturer Part Number: EM357-RTR
• Description: IC RF TXRX ZIGBEE 192KB 48QFN
• Manufacturer: Ember

Specifications of EM357-RTR

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 26mA
• Current - Transmitting: 31mA
• Data Interface: PCB, Surface Mount
• Memory Size: 192kB Flash, 12kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1011-2

SCx_DMASTAT
SC1_DMASTAT
Serial DMA Status Register
SC2_DMASTAT
Serial DMA Status Register
Bitname
SC_RXSSEL
SC_RXFRMB
SC_RXFRMA
SC_RXPARB
SC_RXPARA
SC_RXOVFB
SC_RXOVFA
SC_TXACTB
SC_TXACTA
SC_RXACTB
SC_RXACTA
SC_RXPARB
31
23
15
0
0
0
7
SC_RXPARA
30
22
14
6
0
0
0
Bitfield
[12:10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
SC_RXOVFB
29
21
13
5
0
0
0
Access
R
R
R
R
R
R
R
R
R
R
R
Status of the receive count saved in SCx_RXCNTSAVED (SPI slave mode) when nSSEL
FIFO. Neither receive buffer was capable of accepting any more bytes (unloaded), and
the FIFO filled up. Buffer B was the next buffer to load, and when it drained the FIFO the
overrun error was passed up to the DMA and flagged with this bit. Cleared the next time
buffer B is loaded and when the receive DMA is reset.
FIFO. Neither receive buffer was capable of accepting any more bytes (unloaded), and
the FIFO filled up. Buffer A was the next buffer to load, and when it drained the FIFO the
overrun error was passed up to the DMA and flagged with this bit. Cleared the next time
buffer A is loaded and when the receive DMA is reset.
This bit is set when DMA transmit buffer B is active.
This bit is set when DMA receive buffer B is active.
Description
deasserts. Cleared when a receive buffer is loaded and when the receive DMA is reset.
0: No count was saved because nSSEL did not deassert.
2: Buffer A's count was saved, nSSEL deasserted once.
3: Buffer B's count was saved, nSSEL deasserted once.
6: Buffer A's count was saved, nSSEL deasserted more than once.
7: Buffer B's count was saved, nSSEL deasserted more than once.
1, 4, 5: Reserved.
This bit is set when DMA receive buffer B reads a byte with a frame error from the receive
FIFO. It is cleared the next time buffer B is loaded or when the receive DMA is reset. (SC1
in UART mode only)
This bit is set when DMA receive buffer A reads a byte with a frame error from the receive
FIFO. It is cleared the next time buffer A is loaded or when the receive DMA is reset. (SC1
in UART mode only)
This bit is set when DMA receive buffer B reads a byte with a parity error from the receive
FIFO. It is cleared the next time buffer B is loaded or when the receive DMA is reset. (SC1
in UART mode only)
This bit is set when DMA receive buffer A reads a byte with a parity error from the receive
FIFO. It is cleared the next time buffer A is loaded or when the receive DMA is reset. (SC1
in UART mode only)
This bit is set when DMA receive buffer B was passed an overrun error from the receive
This bit is set when DMA receive buffer A was passed an overrun error from the receive
This bit is set when DMA transmit buffer A is active.
This bit is set when DMA receive buffer A is active.
SC_RXOVFA
28
20
12
4
0
0
Final
8-35
SC_TXACTB
SC_RXSSEL
27
19
11
3
0
0
SC_TXACTA
26
18
10
0
0
2
Address: 0x4000C82C Reset: 0x0
Address: 0x4000C02C Reset: 0x0
EM351 / EM357
SC_RXFRMB
SC_RXACTB
25
17
0
0
9
1
120-035X-000G
SC_RXFRMA
SC_RXACTA
24
16
0
0
8
0