EM357-RTR Ember, EM357-RTR Datasheet - Page 128

• Manufacturer Part Number: EM357-RTR
• Description: IC RF TXRX ZIGBEE 192KB 48QFN
• Manufacturer: Ember

Specifications of EM357-RTR

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 26mA
• Current - Transmitting: 31mA
• Data Interface: PCB, Surface Mount
• Memory Size: 192kB Flash, 12kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1011-2

update event (UEV), depending on the auto-reload buffer enable bit (TIM_ARBE) in the TIMx_CR1 register. The
UEV is generated when both the counter reaches the overflow (or underflow when down-counting) and when
the TIM_UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. UEV generation is
described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit
(TIM_CEN) in the TIMx_CR1 register is set. Refer also to the slave mode controller description in the Timers
and External Trigger Synchronization section to get more details on counter enabling.
Note that the actual counter enable signal CNT_EN is set one clock cycle after TIM_CEN.
Note: When the EM35x enters debug mode and the ARM
run normally.
9.3.1.1
The prescaler can divide the counter clock frequency by power of two from 1 through 32768. It is based on a
16-bit counter controlled through the 4-bit TIM_PSCEXP bit field in the TIMx_PSC register. The factor by which
the counter is divided is two raised to the power TIM_PSCEXP (2
It can be changed on the fly as this control register is buffered. The new prescaler ratio is used starting at the
next UEV.
Figure 9-2 gives an example of the counter behavior when the prescaler ratio is changed on the fly.
9.3.2
9.3.2.1
In up-counting mode, the counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register),
then restarts from 0 and generates a counter overflow event.
A UEV can be generated at each counter overflow, by setting the TIM_UG bit in the TIMx_EGR register, or by
using the slave mode controller.
Software can disable the UEV by setting the TIM_UDIS bit in the TIMx_CR1 register, to avoid updating the
shadow registers while writing new values in the buffer registers. No UEV will occur until the TIM_UDIS bit is
written to 0. Both the counter and the prescaler counter restart from 0, but the prescale rate does not
change. In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit generates a UEV
Prescaler
Counter Modes
Up-Counting Mode
Figure 9-2. Counter Timing Diagram with Prescaler Division Change from 1 to 4
Final
9-4
®
Cortex
TIM_PSCEXP
TM
-M3 core is halted, the counters continue to
).
120-035X-000G