EM357-RTR Ember, EM357-RTR Datasheet - Page 97

IC RF TXRX ZIGBEE 192KB 48QFN

EM357-RTR

Manufacturer Part Number
EM357-RTR
Description
IC RF TXRX ZIGBEE 192KB 48QFN
Manufacturer
Ember
Datasheets

Specifications of EM357-RTR

Frequency
2.4GHz
Data Rate - Maximum
250kbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
5dBm
Sensitivity
-100dBm
Voltage - Supply
2.1 V ~ 3.6 V
Current - Receiving
26mA
Current - Transmitting
31mA
Data Interface
PCB, Surface Mount
Memory Size
192kB Flash, 12kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
636-1011-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EM357-RTR
Manufacturer:
SILICON
Quantity:
3 000
Part Number:
EM357-RTR
Manufacturer:
SILICON
Quantity:
20 000
Part Number:
EM357-RTR
0
Company:
Part Number:
EM357-RTR
Quantity:
6 000
SCx_TWISTAT
SC1_TWISTAT
TWI Status Register
SC2_TWISTAT
TWI Status Register
Bitname
SC_TWICMDFIN
SC_TWIRXFIN
SC_TWITXFIN
SC_TWIRXNAK
31
23
15
0
0
0
7
0
To enable CPU interrupts, set the desired interrupt bits in the second-level INT_SCxCFG register, and enable
the top-level SCx interrupt in the NVIC by writing the INT_SCx bit in the INT_CFGSET register.
8.5.5
Refer to Registers (in the SPI Master Mode section) for a description of the SCx_DATA, SCx_RATELIN, and
SCx_RATEEXP registers.
30
22
14
6
0
0
0
0
Character transmitted (0 to 1 transition of SC_TWITXFIN)
Character received (0 to 1 transition of SC_TWIRXFIN)
Received and lost character while receive FIFO was full (receive overrun error)
Transmitted character while transmit FIFO was empty (transmit underrun error)
Bitfield
[3]
[2]
[1]
[0]
Registers
29
21
13
5
0
0
0
0
Access
R
R
R
R
This bit is set when a START or STOP command completes. It clears on the next TWI bus
Description
activity.
This bit is set when a byte is received. It clears on the next TWI bus activity.
This bit is set when a byte is transmitted. It clears on the next TWI bus activity.
This bit is set when a NACK is received from the slave. It clears on the next TWI bus
activity.
28
20
12
4
0
0
0
0
Final
8-22
SC_TWICMDFIN
27
19
11
3
0
0
0
SC_TWIRXFIN
26
18
10
0
0
0
2
Address: 0x4000C844 Reset: 0x0
Address: 0x4000C044 Reset: 0x0
EM351 / EM357
SC_TWITXFIN
25
17
0
0
9
0
1
120-035X-000G
SC_TWIRXNAK
24
16
0
0
8
0
0

Related parts for EM357-RTR