ADF7020BCPZ Analog Devices Inc, ADF7020BCPZ Datasheet
ADF7020BCPZ
Specifications of ADF7020BCPZ
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ADF7020BCPZ Summary of contents
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FEATURES Low power, low IF transceiver Frequency bands 431 MHz to 478 MHz 862 MHz to 956 MHz Data rates supported 0.15 kbps to 200 kbps, FSK 0.15 kbps to 64 kbps, ASK 2 3.6 V power supply ...
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ADF7020 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications..................................................................................... 5 Timing Characteristics..................................................................... 8 Timing Diagrams.......................................................................... 8 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and ...
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REVISION HISTORY 8/07—Rev Rev. B Changes to Features ..........................................................................1 Changes to General Description .....................................................4 Changes to Table 1 ............................................................................5 Changes to Table 2 ............................................................................8 Changes to Reference Input Section.............................................15 Changes to N Counter Section......................................................16 Changes to Choosing Channels ...
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ADF7020 GENERAL DESCRIPTION The ADF7020 is a low power, highly integrated FSK/ASK/OOK transceiver designed for operation in the license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz, as well as the proposed Japanese RFID band at 950 MHz. ...
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SPECIFICATIONS VDD = 2 3.6 V, GND = All measurements are performed using the EVAL-ADF7020DBZx using the PN9 data sequence, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS Frequency Ranges (Direct Output) ...
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ADF7020 Parameter 7 LNA and Mixer, Input IP3 Enhanced Linearity Mode Low Current Mode High Sensitivity Mode 8 Rx Spurious Emissions AFC Pull-In Range at 868 MHz/915 MHz Pull-In Range at 433 MHz Response Time Accuracy CHANNEL FILTERING Adjacent Channel ...
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Parameter REFERENCE INPUT Crystal Reference External Oscillator Load Capacitance Crystal Start-Up Time Input Level ADC PARAMETERS INL DNL TIMING INFORMATION Chip Enabled to Regulator Ready Chip Enabled to RSSI Ready Turnaround Time LOGIC INPUTS Input High Voltage, ...
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ADF7020 TIMING CHARACTERISTICS VDD = 3 V ± 10%, VGND = 25°C, unless otherwise noted. Guaranteed by design, not production tested. A Table 2. Parameter Limit MIN t > >10 ...
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DATA RATE/32 RxCLK RxDATA DATA TxCLK TxDATA DATA FETCH SAMPLE NOTES 1. TxCLK ONLY AVAILABLE IN GFSK MODE. 1/DATA RATE Figure 4. RxData/RxCLK Timing Diagram 1/DATA RATE Figure 5. TxData/TxCLK Timing Diagram Rev Page 9 of ...
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ADF7020 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter 1 VDD to GND Analog I/O Voltage to GND Digital I/O Voltage to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 VCOIN The tuning voltage on this pin determines the output frequency of the voltage-controlled oscillator (VCO). The higher the tuning voltage, the higher the output ...
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ADF7020 Pin No. Mnemonic Description 27 SREAD Serial Data Output. This pin is used to feed readback data from the ADF7020 to the microcontroller. The SCLK input is used to clock each readback bit (AFC, ADC readback) from the SREAD ...
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TYPICAL PERFORMANCE CHARACTERISTICS CARRIER POWER –0.28dBm ATTEN 0.00dB REF –70.00dBc/Hz 10.00 dB/DIV 1 1kHz FREQUENCY OFFSET Figure 7. Phase Noise Response at 868.3 MHz, VDD = 3.0 V, ICP = 1 GFSK 70 ...
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ADF7020 20 9µA 15 11µ –5 –10 –15 –20 – SETTING Figure 13. PA Output Power vs. Setting 80 70 ...
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FREQUENCY SYNTHESIZER REFERENCE INPUT The on-board crystal oscillator circuitry (see Figure 19) can use an inexpensive quartz crystal as the PLL reference. The oscilla- tor circuit is enabled by setting R1_DB12 high enabled by default on power-up and ...
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ADF7020 Voltage Regulators The ADF7020 contains four regulators to supply stable voltages to the part. The nominal regulator voltage is 2.3 V. Each regulator should have a 100 nF capacitor connected between CREGx and GND. When CE is high, the ...
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VCO Bias Current VCO bias current can be adjusted using Bit R1_DB19 to Bit R1_DB16. To ensure VCO oscillation, the minimum bias current setting under all conditions is 0xA. VCO BIAS TO N R1_DB[16:19] DIVIDER LOOP FILTER VCO ÷2 ÷2 ...
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ADF7020 TRANSMITTER RF OUTPUT STAGE The PA of the ADF7020 is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver dBm into a 50 Ω load at a maximum frequency of 956 ...
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Gaussian Frequency Shift Keying (GFSK) Gaussian frequency shift keying reduces the bandwidth occu- pied by the transmitted spectrum by digitally prefiltering the TxData. A TxCLK output line is provided from the ADF7020 for synchronization of TxData from the microcontroller. The ...
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ADF7020 RECEIVER RF FRONT END The ADF7020 is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low external component count and does not suffer from power line- induced interference problems. Figure 28 ...
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RSSI/AGC The RSSI is implemented as a successive compression log amp following the baseband channel filtering. The log amp achieves ±3 dB log linearity. It also doubles as a limiter to convert the signal-to-digital levels for the FSK demodulator. The ...
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ADF7020 FREQUENCY CORRELATOR IF I LIMITERS – DEV DEV R6_DB[4:13] R6_DB[14] Figure 30. FSK Correlator/Demodulator Block Diagram Postdemodulator Filter A second-order, digital low-pass filter removes excess noise from the demodulated bit stream at the ...
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Table 9. Register Settings Setting Name Register Address Postdemod_BW_Setting R4_DB[6:15] Discriminator_BW R6_DB[4:13] Dot_Product R6_DB14 RxData_Invert R6_DB29 1 The latest version of the ADF7020 configuration software can aid in calculating register settings. LINEAR FSK DEMODULATOR Figure 31 shows a block ...
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ADF7020 Internal AFC The ADF7020 supports a real-time internal automatic frequency control loop. In this mode, an internal control loop automatically monitors the frequency error and adjusts the synthesizer N divider using an internal PI control loop. The internal AFC ...
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APPLICATIONS INFORMATION LNA/PA MATCHING The ADF7020 exhibits optimum performance in terms of sensitivity, transmit power, and current consumption only if its RF input and output ports are properly matched to the antenna impedance. For cost-sensitive applications, the ADF7020 is equipped ...
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ADF7020 The procedure typically requires several iterations until an acceptable compromise is reached. The successful implementation of a combined LNA/PA matching network for the ADF7020 is critically dependent on the availability of an accurate electrical model for the PC board. ...
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CAL AT +25° CAL AT +85° 3. 25kHz 20 WANTED SIGNAL: INTERFERER SIGNAL: RF FREQ = 430MHz RF FREQ = 429.8MHz MODULATION = 2FSK MODULATION = 2FSK DATA RATE = ...
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ADF7020 POWER CONSUMPTION AND BATTERY LIFETIME CALCULATIONS Average Power Consumption can be calculated using Average Power Consumption = ( )/( PowerDown ON OFF 19mA TO 22mA 14mA XTAL t 0 3.65mA 2.0mA REG. READY ...
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TO 30mA 14mA 3.65mA 2.0mA REG. READY WR0 WR1 XTAL + VCO Figure 40. Tx Programming Sequence and Timing Diagram WR2 TxDATA Rev ...
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ADF7020 T-STAGE LC ANTENNA FILTER CONNECTION LOOP FILTER CVCO CAP VDD 1 VCOIN MATCHING 2 CREG1 3 VDD VDD1 4 RFOUT 5 RFGND 6 RFIN 7 RFINB 8 R LNA 9 VDD VDD4 10 RSET 11 CREG4 12 GND4 RLNA ...
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SERIAL INTERFACE The serial interface allows the user to program the fourteen 32-bit registers using a 3-wire interface (SCLK, SDATA, and SLE). Signals should be CMOS compatible. The serial interface is powered by the regulator and, therefore, is inactive when ...
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ADF7020 REGISTERS REGISTER 0—N REGISTER MUXOUT 8-BIT INTEGER-N TRANSMIT/ TR1 RECEIVE 0 TRANSMIT 1 RECEIVE PLE1 PLL ENABLE 0 PLL OFF 1 PLL MUXOUT REGULATOR READY (DEFAULT ...
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REGISTER 1—OSCILLATOR/FILTER REGISTER FREQUENCY VA2 VA1 OF OPERATION 0 0 850 TO 920 0 1 860 TO 930 1 0 870 TO 940 1 1 880 TO 950 VB4 VB3 ...
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ADF7020 REGISTER 2—TRANSMIT MODULATION REGISTER (ASK/OOK MODE) GFSK MOD CONTROL PA BIAS IC2 IC1 MC3 MC2 MC1 DI1 0 TxDATA 1 TxDATA PA2 PA1 PA BIAS 0 0 5µ 7µ 9µA ...
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REGISTER 2—TRANSMIT MODULATION REGISTER (FSK MODE) GFSK MOD CONTROL PA BIAS IC2 IC1 MC3 MC2 MC1 DI1 0 TxDATA 1 TxDATA PA2 PA1 PA BIAS 0 0 5µ 7µ 9µA 1 ...
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ADF7020 REGISTER 2—TRANSMIT MODULATION REGISTER (GFSK/GOOK MODE) GFSK MOD CONTROL PA BIAS DI1 0 TxDATA 1 TxDATA PA2 PA1 PA BIAS 5µ 7µ 9µ 11µA 1 IC2 IC1 ...
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REGISTER 3—RECEIVER CLOCK REGISTER SEQUENCER CLOCK DIVIDE SK8 SK7 . . Register 3—Receiver Clock Register Comments • Baseband offset clock frequency (BBOS_CLK) must be greater than ...
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ADF7020 REGISTER 4—DEMODULATOR SETUP REGISTER DEMOD MODE LM2 LM1 DL8 DEMOD LOCK/SYNC WORD MATCH SERIAL PORT CONTROL – FREE RUNNING SERIAL PORT CONTROL – LOCK THRESHOLD SYNC WORD ...
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REGISTER 5—SYNC BYTE REGISTER Register 5—Sync Byte Register Comments • Sync byte detect is enabled by programming Bits R4_DB[25:23] to 010 or 011. • This register allows a 24-bit sync byte sequence to be stored internally. If the sync byte ...
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ADF7020 REGISTER 6—CORRELATOR/DEMODULATOR REGISTER Rx RESET IF FILTER DIVIDER ML1 0 1 RxDATA RI1 INVERT 0 RxDATA 1 RxDATA RxRESET 0 NORMAL OPPERATION FC9 1 DEMOD RESET RxRESET . 0 NORMAL OPPERATION . 1 1 CDR ...
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REGISTER 7—READBACK SETUP REGISTER RB3 READBACK 0 DISABLED 1 ENABLED Register 7—Readback Setup Register Comments • Readback of the measured RSSI value is valid only in Rx mode. To enable readback of the battery voltage, the temperature sensor, or the ...
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ADF7020 REGISTER 8—POWER-DOWN TEST REGISTER DB13 DB12 PD7 SW1 PD7 PA (Rx MODE OFF SW1 Tx/Rx SWITCH 0 DEFAULT (ON) 1 OFF LR2 LR1 RSSI MODE X 0 RSSI OFF X 1 RSSI ON PD6 ...
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REGISTER 9—AGC REGISTER DIGITAL FILTER TEST IQ GAIN FI1 FILTER CURRENT 0 LOW 1 HIGH FG2 FG1 FILTER GAIN INVALID LG2 Register 9—AGC Register Comments ...
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ADF7020 REGISTER 10—AGC 2 REGISTER I/Q PHASE ADJUST SIQ2 SELECT IQ SIQ2 0 PHASE TO I CHANNEL 0 1 PHASE TO Q CHANNEL 1 Register 10—AGC 2 Register Comments • This register is not used under normal operating conditions. • ...
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REGISTER 12—TEST REGISTER ANALOG TEST MUX P PRESCALER 0 4/5 (DEFAULT) 1 8/9 CS1 CAL SOURCE 0 INTERNAL 1 SERIAL IF BW CAL Register 12—Test Register Comments This register does not need to be written to in normal operation. The ...
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ADF7020 REGISTER 13—OFFSET REMOVAL AND SIGNAL GAIN REGISTER TEST DAC GAIN TEST DAC OFFSET REMOVAL Register 13—Offset Removal and Signal Gain Register Comments • Because the linear demodulator’s output is proportional to frequency, it usually consists of an offset combined ...
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... MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 ADF7020BCPZ −40°C to +85°C 1 ADF7020BCPZ-RL −40°C to +85°C 1 ADF7020BCPZ-RL7 −40°C to +85°C EVAL-ADF70xxMBZ EVAL-ADF70xxMBZ2 EVAL-ADF7020DBZ1 EVAL-ADF7020DBZ2 EVAL-ADF7020DBZ3 RoHS Compliant Part. 7.00 BSC SQ 0.60 MAX 37 36 TOP 6.75 ...
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ADF7020 NOTES ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05351-0-8/07(B) Rev Page ...