CYWUSB6934-48LTXC Cypress Semiconductor Corp, CYWUSB6934-48LTXC Datasheet - Page 10

IC WIRELESS USB 2.4GHZ 48VQFN

CYWUSB6934-48LTXC

Manufacturer Part Number
CYWUSB6934-48LTXC
Description
IC WIRELESS USB 2.4GHZ 48VQFN
Manufacturer
Cypress Semiconductor Corp
Series
WirelessUSB™r
Datasheet

Specifications of CYWUSB6934-48LTXC

Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Frequency
2.4GHz
Data Rate - Maximum
62.5kbps
Modulation Or Protocol
GFSK
Applications
General Purpose
Power - Output
0dBm
Sensitivity
-90dBm
Voltage - Supply
2.7 V ~ 3.6 V
Current - Receiving
57.7mA
Current - Transmitting
69.1mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
0°C ~ 70°C
Wireless Frequency
2.4 GHz
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2984

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CYWUSB6934-48LTXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Table 8. SERDES Control
Table 9. Receive SERDES Interrupt Enable
Document 38-16007 Rev. *J
Bit
7:4 Reserved
2:0 EOF Length
Bit
Underflow B
7
6
5
4
3
Underflow B
Overflow B
EOF B
Full B
SERDES
Enable
7
7
Name
Addr: 0x06
Addr: 0x07
Name
Overflow B
The Underflow B bit is used to enable the interrupt associated with an underflow condition with the Receive
SERDES Data B register (Reg 0x0B)
1 = Underflow B interrupt enabled for Receive SERDES Data B
0 = Underflow B interrupt disabled for Receive SERDES Data B
An underflow condition occurs when attempting to read the Receive SERDES Data B register (Reg 0x0B) when
it is empty.
The Overflow B bit is used to enable the interrupt associated with an overflow condition with the Receive
SERDES Data B register (Reg 0x0B)
1 = Overflow B interrupt enabled for Receive SERDES Data B
0 = Overflow B interrupt disabled for Receive SERDES Data B
An overflow condition occurs when new received data is written into the Receive SERDES Data B register (Reg
0x0B) before the prior data is read out.
The End of Frame B bit is used to enable the interrupt associated with the Channel B Receiver EOF condition.
1 = EOF B interrupt enabled for Channel B Receiver.
0 = EOF B interrupt disabled for Channel B Receiver.
The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit
has been detected, and then the number of invalid bits in the frame exceeds the number in the EOF length field.
If 0 is the EOF length, and EOF condition will occur at the first invalid bit after a valid reception. This IRQ is
cleared by reading the receive status register
The Full B bit is used to enable the interrupt associated with the Receive SERDES Data B register (Reg 0x0B)
having data placed in it.
1 = Full B interrupt enabled for Receive SERDES Data B
0 = Full B interrupt disabled for Receive SERDES Data B
A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data
B register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether
or not a complete byte has been received.
6
6
These bits are reserved and should be written with zeroes.
The SERDES Enable bit is used to switch between bit-serial mode and SERDES mode.
1 = SERDES enabled.
0 = SERDES disabled, bit-serial mode enabled.
When the SERDES is enabled data can be written to and read from the IC one byte at a time, through the
use of the SERDES Data registers. The bit-serial mode requires bits to be written one bit at a time through
the use of the DIO/DIOVAL pins, refer to section 3.2. It is recommended that SERDES mode be used to
avoid the need to manage the timing required by the bit-serial mode.
The End of Frame Length bits are used to set the number of sequential bit times for an inter-frame gap
without valid data before an EOF event will be generated. When in receive mode and a valid bit has been
received the EOF event can then be identified by the number of bit times that expire without correlating any
new data. The EOF event causes data to be moved to the proper SERDES Data Register and can also be
used to generate interrupts. If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a
valid reception.
Reserved
EOF B
5
5
Full B
REG_SERDES_CTL
REG_RX_INT_EN
4
4
Underflow A
SERDES
Description
Enable
Description
3
3
Overflow A
2
2
EOF Length
EOF A
1
1
CYWUSB6934
CYWUSB6932
Default: 0x00
Default: 0x03
Page 10 of 33
Full A
0
0
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