CYWUSB6934-48LTXC Cypress Semiconductor Corp, CYWUSB6934-48LTXC Datasheet - Page 12

• Manufacturer Part Number: CYWUSB6934-48LTXC
• Description: IC WIRELESS USB 2.4GHZ 48VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: WirelessUSB™r

Specifications of CYWUSB6934-48LTXC

• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: GFSK
• Applications: General Purpose
• Power - Output: 0dBm
• Sensitivity: -90dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Receiving: 57.7mA
• Current - Transmitting: 69.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Wireless Frequency: 2.4 GHz
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2984

Note
Document 38-16007 Rev. *J
4. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The status
Bit
4
3
2
1
0
bits are affected by TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the receive status will read 0 if the IC is not in receive mode. These registers are
read-only.
Full B
Valid A
Flow Violation
A
EOF A
Full A
Name
The Full B bit is used to signal when the Receive SERDES Data B register (Reg 0x0B) is filled with data.
1 = Receive SERDES Data B full interrupt pending.
0 = No Receive SERDES Data B full interrupt pending.
A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES
Data B register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs
whether or not a complete byte has been received.
The Valid A bit is true when all of the bits in the Receive SERDES Data A Register (Reg 0x09) are valid.
1 = All bits are valid for Receive SERDES Data A.
0 = Not all bits are valid for Receive SERDES Data A.
When data is written into the Receive SERDES Data A register (Reg 0x09) this bit is set if all of the bits within
the byte that has been written are valid. This bit cannot generate an interrupt.
The Flow Violation A bit is used to signal whether an overflow or underflow condition has occurred for the
Receive SERDES Data A register (Reg 0x09).
1 = Overflow/underflow interrupt pending for Receive SERDES Data A.
0 = No overflow/underflow interrupt pending for Receive SERDES Data A.
Overflow conditions occur when the radio loads new data into the Receive SERDES Data A register (Reg
0x09) before the prior data has been read. Underflow conditions occur when trying to read the Receive
SERDES Data A register (Reg 0x09) when the register is empty. This bit is cleared by reading the Receive
Interrupt Status register (Reg 0x08)
The End of Frame A bit is used to signal whether an EOF event has occurred on the Channel A receive.
1 = EOF interrupt pending for Channel A.
0 = No EOF interrupt pending for Channel A.
An EOF condition occurs for the Channel A Receiver when receive has begun and then the number of bit
times specified in the SERDES Control register (0x06) elapse without any valid bits being received. This bit
is cleared by reading the Receive Interrupt Status register (Reg 0x08).
The Full A bit is used to signal when the Receive SERDES Data A register (Reg 0x09) is filled with data.
1 = Receive SERDES Data A full interrupt pending.
0 = No Receive SERDES Data A full interrupt pending.
A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES
Data A Register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs
whether or not a complete byte has been received.
Description
CYWUSB6934
CYWUSB6932
Page 12 of 33
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