CYWUSB6935-48LFXC Cypress Semiconductor Corp, CYWUSB6935-48LFXC Datasheet
CYWUSB6935-48LFXC
Specifications of CYWUSB6935-48LFXC
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CYWUSB6935-48LFXC Summary of contents
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... The CYWUSB6935 transceiver is a single-chip 2.4-GHz Direct Sequence Spread Spectrum (DSSS) Gaussian Frequency Shift Keying (GFSK) baseband modem radio that connects directly to a microcontroller via a simple serial peripheral interface. The CYWUSB6935 is offered in an industrial temperature range 48-pin QFN and a commercial temperature range 48- pin QFN. 3.0 Applications • ...
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... The radio and baseband are both code- and frequency-agile. Forty-nine spreading codes selected for optimal performance (Gold codes) are supported across 78 1-MHz channels yielding a theoretical spectral capacity of 3822 channels. The CYWUSB6935 supports a range meters or more. 4.1 2.4-GHz Radio The receiver and transmitter are a single-conversion, low- ...
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... The Radio Frequency (RF) circuitry has on-chip decoupling capacitors. The CYWUSB6935 is powered from a 2.7V to 3.6V DC supply. The CYWUSB6935 can be shutdown to a fully static state using the PD pin. Below are the requirements for the crystal to be directly connected to X13IN and X13: • ...
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... Address Figure 5-1. SPI Transaction Format Figure 5-2. SPI Single Read Sequence Figure 5-3. SPI Burst Read Sequence addr data from Figure 5-4. SPI Single Write Sequence from Figure 5-5. SPI Burst Write Sequence CYWUSB6935 Byte 1+N [7:0] Data fro Page ...
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... Interrupts The CYWUSB6935 features three sets of interrupts: transmit, received, and a wake interrupt. These interrupts all share a single pin (IRQ), but can be independently enabled/disabled. In transmit mode, all receive interrupts are automatically disabled, and in receive mode all transmit interrupts are automatically disabled. However, the contents of the enable registers are preserved when switching between transmit and receive modes ...
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... Application Examples Figure 6-1 shows a block diagram example of a typical battery powered device using the CYWUSB6935 chip. LDO/ DC2DC + - Battery PSoC Application 8-bit MCU Hardware ALAR irelessU Document 38-16008 Rev. *A Figure 6-2 shows an application example of a WirelessUSB LR alarm system where a single hub node is connected to an alarm panel ...
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... Register Descriptions Table 7-1 displays the list of registers inside the CYWUSB6935 that are addressable through the SPI interface. All registers are read and writable, except where noted. Table 7-1. CYWUSB6935 Register Map Register Name Revision ID Reserved Reserved Control Data Rate ...
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... Bit Name Description 7:0 Reserved These bits are reserved and should be written with zeroes. Document 38-16008 Rev. *A REG_ID Figure 7-1. Revision ID Register RESERVED Reserved Figure 7-2. Reserved RESERVED Reserved Figure 7-3. Reserved CYWUSB6935 Default: 0x07 Product ID Default: 0x00 Default: 0x00 Page ...
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... Reserved This bit is reserved and should be written with a one. 0 Reserved This bit is reserved and should be written with a zero. Document 38-16008 Rev. *A REG_CONTROL Auto Syn Auto Internal PA Select Count Select Disable Figure 7-4. Control CYWUSB6935 Default: 0x00 Internal PA Reserved Reserved Enable Page ...
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... The following Reg 0x04, bits 2:0 values are not valid: • 001–Not Valid • 010–Not Valid • 011–Not Valid • 111–Not Valid Document 38-16008 Rev. *A REG_DATA_RATE Figure 7-5. Data Rate CYWUSB6935 Default: 0x00 2 1 Code Width Data Rate Sample Rate Page ...
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... the EOF length, an EOF condition will occur at the first invalid bit after a valid reception. Document 38-16008 Rev. *A REG_CONFIG Reserved Figure 7-6. Configuration REG_SERDES_CTL SERDES Enable Figure 7-7. SERDES Control CYWUSB6935 Default: 0x01 IRQ Pin Select Default: 0x03 EOF Length Page ...
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... This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received. Document 38-16008 Rev. *A REG_RX_INT_EN EOF B Full B Underflow A Figure 7-8. Receive SERDES Interrupt Enable CYWUSB6935 Default: 0x00 Overflow A EOF A Full A Page ...
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... TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the receive status will read 0 if the IC is not in receive mode. These registers are read-only. Document 38-16008 Rev. *A REG_RX_INT_STAT EOF B Full B Valid A Figure 7-9. Receive SERDES Interrupt Status CYWUSB6935 Default: 0x00 2 1 Flow Violation A EOF A [3] Page Full A ...
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... Document 38-16008 Rev. *A REG_RX_DATA_A Data Figure 7-10. Receive SERDES Data A REG_RX_VALID_A Valid Figure 7-11. Receive SERDES Valid A REG_RX_DATA_B Data Figure 7-12. Receive SERDES Data B REG_RX_VALID_B Valid Figure 7-13. Receive SERDES Valid B CYWUSB6935 Default: 0x00 Default: 0x00 Default: 0x00 Default: 0x00 Page ...
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... IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in transmit mode. These registers are read-only. Document 38-16008 Rev. *A REG_TX_INT_EN Underflow Figure 7-14. Transmit SERDES Interrupt Enable REG_TX_INT_STAT Underflow Figure 7-15. Transmit SERDES Interrupt Status CYWUSB6935 Default: 0x00 Overflow Done Empty Default: 0x00 Overflow Done Empty ...
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... Transmit SERDES Valid register (Reg 0x10) will send half a byte. Document 38-16008 Rev. *A REG_TX_DATA Data Figure 7-16. Transmit SERDES Data REG_TX_VALID Valid Figure 7-17. Transmit SERDES Valid REG_PN_CODE Address 0x17 Address 0x16 Address 0x13 Address 0x12 Figure 7-18. PN Code CYWUSB6935 Default: 0x00 Default: 0x00 Default: 0x1E8B6A3DE0E9B222 Address 0x15 ...
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... Document 38-16008 Rev. *A REG_THRESHOLD_L Threshold Low Figure 7-19. Threshold Low REG_THRESHOLD_H Threshold High Figure 7-20. Threshold High CYWUSB6935 Default: 0x08 Default: 0x38 Page ...
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... No Device Reset. Document 38-16008 Rev. *A REG_WAKE_EN Reserved Figure 7-21. Wake Enable REG_WAKE_STAT Reserved Figure 7-22. Wake Status REG_ANALOG_CTL Reserved Reserved Enable Figure 7-23. Analog Control CYWUSB6935 Default: 0x00 Wakeup Enable Default: 0x01 Wakeup Status Default: 0x00 Output PA Invert Reset Enable Page ...
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... See Table 4-1 for typical output power steps based on the PA Bias bit settings. Document 38-16008 Rev. *A REG_CHANNEL Channel Figure 7-24. Channel REG_RSSI Valid REG_PA Figure 7-26. Power Control CYWUSB6935 Default: 0x00 Default: 0x00 RSSI [6] Default: 0x00 Bias Page ...
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... These bits are undefined for read operations. 5:0 Reserved These bits are reserved and should be written with zeroes. Document 38-16008 Rev. *A REG_CRYSTAL_ADJ Crystal Adjust Figure 7-27. Crystal Adjust ll y REG_VCO_CAL Reserved Figure 7-28. VCO Calibration CYWUSB6935 Default: 0x00 Default: 0x00 Page ...
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... Document 38-16008 Rev. *A REG_PWR_CTL Reserved Figure 7-29. Reg Power Control REG_CARRIER_DETECT Reserved Figure 7-30. Carrier Detect REG_CLOCK_MANUAL Manual Clock Overrides Figure 7-31. Clock Manual REG_CLOCK_ENABLE Manual Clock Enables Figure 7-32. Clock Enable CYWUSB6935 Default: 0x00 Default: 0x00 Default: 0x00 Default: 0x00 Page ...
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... The MID Read Enable bit in the Analog Control register (Reg 0x20, bit 5) should only be set when reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F). This register is read-only. Document 38-16008 Rev. *A REG_SYN_LOCK_CNT Count Figure 7-33. Synthesizer Lock Count REG_MID Address 0x3E Address 0x3D Figure 7-34. Manufacturing ID CYWUSB6935 Default: 0x64 ...
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... IRQ . Interrupt and SERDES Bypass Mode DIOCLK. N/A Master-Output-Slave-Input Data . SPI data input pin. Hi-Z Master-Input-Slave-Output Data . SPI data output pin. N/A SPI Input Clock . SPI clock. N/A Slave Select Enable . SPI enable 2.7V to 3.6V Ground = Must be tied to Ground. N/A L Must be tied to Ground. CYWUSB6935 Description Page ...
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... RFOUT * E-PAD BOTTOM SIDE Document 38-16008 Rev. *A CYWUSB6935 Top View CYWUSB6935 QFN Figure 8-1. CYWUSB6935, 48 QFN – Top View CYWUSB6935 X13IN 34 PACTL X13OUT 25 SCK Page ...
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... Temperature Under Bias) ....... -40°C to +85° (Ambient Temperature Under Bias) .........0°C to +70°C A +0.3V Ground Voltage ................................................................. (Oscillator or Crystal Frequency) ..................... 13 MHz OSC +0.3V CC Description Conditions < HIGH [13] CYWUSB6935 Operating Conditions [12] Min. Typ. 2.7 3.0 = –100.0 µA V –0 –2.0 mA 2.4 3.0 = 2.0 mA 0.0 2.0 –0.3 < V –1 0. ...
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... SCK must start low, otherwise the success of SPI transactions are not guaranteed. Document 38-16008 Rev. *A Description fro Figure 12-1. SPI Timing Diagram t t SCK_LO S CK_H I (B URST READ) th every 9 S CK_H I data T_VAL CYWUSB6935 Min. Typ. Max. Unit 476 ns 238 ns 158 ns 158 [16 [16] [16] 77 174 ...
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... Minimum IRQ Low Time – 64 chips/bit Document 38-16008 Rev. *A Description Figure 12-3. DIO Receive Timing Diagram _IR _IR Q _LO data _DIO AL_ HLD Figure 12-4. DIO Transmit Timing Diagram CYWUSB6935 Min. Typ. Max. 2.1 2 –0.01 6.1 –0.01 8.2 –0.01 16.1 –0.01 6.1 –0.01 8.2 –0.01 16 ...
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... C = –67 dBm [18 –67 dBm C = –64 dBm ∆ 5,10 MHz ± 2 ppm seven steps, monotonic PN Code Pattern 10101010 PN Code Pattern 11110000 100-kHz resolution bandwidth, –6 dBc CYWUSB6935 Min. Typ. Max. Unit 2.400 2.483 GHz –3 ) –86 –95 dBm –20 –7 dBm ...
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... A wakeup event is triggered when the PD pin is deasserted. Figure 12-6 illustrates a wakeup event configured to trigger an IRQ pin event via the Wake Enable register (Reg 0x1C, bit 0=1). Document 38-16008 Rev. *A [22] [23] [25] assert (wake interrupt) to within ±10 ppm Figure 12-5. Power On Reset/Reset Timing Figure 12-6. Sleep / Wake Timing CYWUSB6935 Conditions Min. Typ 2000 2.7V 1300 cc 1 1300 2000 10 50 2000 ...
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... R 500 3.00 CC Figure 12-7. AC Test Loads and Waveforms for Digital Pins 13.0 Ordering Information Part Number Radio CYWUSB6935-48LFXI Transceiver CYWUSB6935-48LFXC Transceiver Document 38-16008 Rev. *A OUTPUT 5 pF INCLUDING JIG AND SCOPE Typical Unit V CC Ω Ω GND Ω Rise time: 1 V/ns ...
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... C 1.00 MAX. 0.05 MAX. 0.80 MAX. 0.20 REF. 6.90 7.10 6.70 6.80 0.30-0.45 0°-12° C SEATING PLANE SIDE VIEW Figure 14-1. 48-pin Lead-Free QFN 7 × LY48 CYWUSB6935 X 0.23±0.05 PIN1 ID 0. 0.45 E-PAD Y 0.42±0.18 0.50 5.45 5.55 BOTTOM VIEW E-PAD SIZE PADDLE SIZE (X, Y MAX ...
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... Document History Page Document Title: CYWUSB6935 WirelessUSB™ LR 2.4-GHz DSSS Radio SoC Document Number: 38-16008 REV. ECN NO. Issue Date ** 207428 See ECN *A 275349 See ECN Document 38-16008 Rev. *A Orig. of Change TGE New data sheet ZTK Updated REG_DATA_RATE (0x04), 111 - Not Valid ...