CYWUSB6935-48LFXC Cypress Semiconductor Corp, CYWUSB6935-48LFXC Datasheet - Page 26

• Manufacturer Part Number: CYWUSB6935-48LFXC
• Description: IC USB WIRELESS 2.4GHZ 48VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYWUSB6935-48LFXC

• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: AMR, ISM, RKE
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Receiving: 57.7mA
• Current - Transmitting: 69.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Transmitting Current: 69.1mA
• Data Rate: 62.5Kbps
• Frequency Range: 2.4GHz To 2.483GHz
• Modulation Type: GFSK
• Rf Ic Case Style: QFN
• No. Of Pins: 48
• Supply Voltage Range: 2.7V To 3.6V
• Operating: RoHS Compliant
• Sensitivity Dbm: -95dBm
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1625

Document #: 38-16008 Rev. *E
Table 38. DIO Interface
t
t
t
t
t
t
t
t
t
t
TX_DIOVAL_SU
TX_DIO_SU
TX_DIOVAL_HLD
TX_DIO_HLD
TX_IRQ_HI
TX_IRQ_LO
RX_DIOVAL_VLD
RX_DIO_VLD
RX_IRQ_HI
RX_IRQ_LO
Transmit
Receive
Parameter
D IO V A L
D IO V A L
D IO /
IR Q
D IO /
IR Q
DIOVAL Set-up Time
DIO Set-up Time
DIOVAL Hold Time
DIO Hold Time
Minimum IRQ High Time – 32 chips/bit DDR
Minimum IRQ High Time – 32 chips/bit
Minimum IRQ High Time – 64 chips/bit
Minimum IRQ Low Time – 32 chips/bit DDR
Minimum IRQ Low Time – 32 chips/bit
Minimum IRQ Low Time – 64 chips/bit
DIOVAL Valid Time – 32 chips/bit DDR
DIOVAL Valid Time – 32 chips/bit
DIOVAL Valid Time – 64 chips/bit
DIO Valid Time – 32 chips/bit DDR
DIO Valid Time – 32 chips/bit
DIO Valid Time – 64 chips/bit
Minimum IRQ High Time – 32 chips/bit DDR
Minimum IRQ High Time – 32 chips/bit
Minimum IRQ High Time – 64 chips/bit
Minimum IRQ Low Time – 32 chips/bit DDR
Minimum IRQ Low Time – 32 chips/bit
Minimum IRQ Low Time – 64 chips/bit
t
R X _ IR Q _ H I
d a ta
Figure 13. DIO Transmit Timing Diagram
Figure 12. DIO Receive Timing Diagram
t
TX _D IO V A L_S U
t
Description
T X _D IO _S U
t
TX _IR Q _H I
t
R X _ D IO V A L _ V L D
t
R X _ D IO _ V L D
t
data
R X _ IR Q _ L O
t
T X _IR Q _LO
t
T X _D IO V A L_H LD
t
T X _D IO _H LD
–0.01
–0.01
–0.01
–0.01
–0.01
–0.01
Min.
2.1
2.1
0
0
d a ta
Typ.
16
32
16
32
16
32
8
8
1
1
1
8
data
CYWUSB6935
Max.
16.1
16.1
6.1
8.2
6.1
8.2
Page 26 of 34
d a ta
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
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