CYWUSB6935-48LFXC Cypress Semiconductor Corp, CYWUSB6935-48LFXC Datasheet - Page 8

• Manufacturer Part Number: CYWUSB6935-48LFXC
• Description: IC USB WIRELESS 2.4GHZ 48VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYWUSB6935-48LFXC

• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: AMR, ISM, RKE
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Receiving: 57.7mA
• Current - Transmitting: 69.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Transmitting Current: 69.1mA
• Data Rate: 62.5Kbps
• Frequency Range: 2.4GHz To 2.483GHz
• Modulation Type: GFSK
• Rf Ic Case Style: QFN
• No. Of Pins: 48
• Supply Voltage Range: 2.7V To 3.6V
• Operating: RoHS Compliant
• Sensitivity Dbm: -95dBm
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1625

Table 4. Revision ID Register
Table 5. Control
Document #: 38-16008 Rev. *E
Bit
Bit
7:4
3:0
7 RX Enable
6 TX Enable
5 PN Code
4 Bypass
3 Auto Internal
2 Internal PA
1 Reserved
0 Reserved
Enable
Select
Internal Syn
Lock Signal
PA Disable
Enable
RX
7
7
Silicon ID
Product ID
Name
Addr: 0x00
Addr: 0x03
Name
Enable
The Receive Enable bit is used to place the IC in receive mode.
1 = Receive Enabled
0 = Receive Disabled
The Transmit Enable bit is used to place the IC in transmit mode.
1 = Transmit Enabled
0 = Transmit Disabled
The Pseudo-Noise Code Select bit selects between the upper or lower half of the 64 chips/bit PN code.
1 = 32 Most Significant Bits of PN code are used
0 = 32 Least Significant Bits of PN code are used
This bit applies only when the Code Width bit is set to 32 chips/bit PN codes (Reg 0x04, bit 2=1).
This bit controls whether the state machine waits for the internal Syn Lock Signal before waiting for the amount
of time specified in the Syn Lock Count register (Reg 0x38), in units of 2 μ s. If the internal Syn Lock Signal is
used then set Syn Lock Count to 25 to provide additional assurance that the synthesizer has settled.
0x38)
It is recommended that the application MCU sets this bit to 1 in order to guarantee a consistent settle time for
the synthesizer.
The Auto Internal PA Disable bit is used to determine the method of controlling the Internal Power Amplifier.
The two options are automatic control by the baseband or by firmware through register writes. For external PA
usage, please see the description of the REG_ANALOG_CTL register (Reg 0x20).
1 = Register controlled Internal PA Enable
0 = Auto controlled Internal PA Enable
When this bit is set to 1, the enabled state of the Internal PA is directly controlled by bit Internal PA Enable (Reg
0x03, bit 2). It is recommended that this bit is set to 0, leaving the PA control to the baseband.
The Internal PA Enable bit is used to enable or disable the Internal Power Amplifier.
1 = Internal Power Amplifier Enabled
0 = Internal Power Amplifier Disabled
This bit only applies when the Auto Internal PA Disable bit is selected (Reg 0x03, bit 3=1), otherwise this bit is
don’t care.
This bit is reserved and should be written with a zero.
This bit is reserved and should be written with a zero.
These are the Silicon ID revision bits. 0000 = Rev A, 0001 = Rev B, etc. These bits are read-only.
These are the Product ID revision bits. Fixed at value 0111. These bits are read-only.
1 = Bypass the Internal Syn Lock Signal and wait the amount of time in Syn Lock Count register (Reg 0x38)
0 = Wait for the Syn Lock Signal and then wait the amount of time specified in Syn Lock Count register (Reg
TX
6
6
Silicon ID
PN Code
Select
5
5
Bypass Internal
Syn Lock
Signal
4
4
REG_CONTROL
REG_ID
Auto Internal
Description
Description
Disable
PA
3
3
Internal PA
Enable
2
2
Product ID
Reserved
1
1
CYWUSB6935
Default: 0x07
Default: 0x00
Reserved
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