MC13213 Freescale Semiconductor, MC13213 Datasheet
MC13213
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... Case 1664-01 71-pin LGA [9x9 mm] Ordering Information Device Device Marking 1 MC13211 13211 1 MC13212 13212 1 MC13213 13213 1 See Table 1 for more details. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 MC1321x Pin Assignment and Connections 8 3 MC1321x Serial Peripheral Interface (SPI 802.15.4 Standard Modem . . . . . . . . . . . . . . 16 5 MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 System Electrical Specification . . . . . . . . . 46 7 Application Considerations ...
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... The 802.15.4 Standard supports star, mesh and cluster tree topologies as well as beaconed networks. • The MC13213 contains 60K of flash and 4KB of RAM and is also intended for use with the Freescale fully compliant 802.15.4 MAC and the fully ZigBee compliant Freescale BeeStack. • ...
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... MC13211R2 -40° to 85° C LGA Tape and Reel MC13212 -40° to 85° C LGA MC13212R2 -40° to 85° C LGA Tape and Reel MC13213 -40° to 85° C LGA MC13213R2 -40° to 85° C LGA Tape and Reel Freescale Semiconductor NOTE Table 1. Orderable Parts Details Memory Options 1KB RAM, ...
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... Up to 60K flash memory with block protection and security and 4K RAM — MC13211: 16KB Flash, 1KB RAM — MC13212: 32KB Flash, 2KB RAM — MC13213: 60KB Flash, 4KB RAM • Low power modes (Wait plus Stop2 and Stop3 modes) • Dedicated serial peripheral interface (SPI) connected internally to 802.15.4 modem • ...
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... Software Features Freescale provides a wide range of software functionality to complement the MC1321x hardware. There are three levels of application solutions: • SMAC • IEEE 802.15.4 Standard-Compliant MAC • SynkroRF • BeeStack • BeeStack Consumer (ZigBee RF4CE) Freescale Semiconductor MC13211/212/213 Technical Data, Rev. 1.8 5 ...
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... Based on the IEEE 802.15.4 Standard • Supports application profiles that define standardized command sets for multi-vendor interoperability • Supports vendor specific extensions to standard application profiles for vendor specific customizing • Supports AES-128 bit encryption 6 MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor ...
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... The MCU contains an internal clock generator (which can be trimmed) that can be used to run the MCU for low power operation. This internal reference is approximately 243 kHz Freescale Semiconductor Analog Receiv er RFIC Timers Frequency ...
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... XTAL2 CLKO EXTAL 16MHz MC1321x 71 TES T Flag opening Flag opening TES Figure 3. MC1321x Pinout (Top View) MC13211/212/213 Technical Data, Rev. 1.8 XTAL PTD4/TPM2CH1 48 47 PTD2/TPM1CH2 70 ATTN 46 VDD 45 GPIO1 44 43 GPIO2 GPIO3 42 GPIO4 PAO_M PAO_P RFIN_P 36 RFIN_M 35 34 CT_Bias VDDA Freescale Semiconductor ...
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... PTC4 Digital Input/Output 17 PTC5 Digital Input/Output 18 PTC6 Digital Input/Output Freescale Semiconductor Table 2. Pin Function Description Description MCU Port A Bit 3 / Keyboard Input Bit 3 MCU Port A Bit 4 / Keyboard Input Bit 4 MCU Port A Bit 5 / Keyboard Input Bit 5 MCU Port A Bit 6 / Keyboard Input Bit 6 MCU Port A Bit 7 / Keyboard Input Bit 7 MCU power supply to ATD Decouple to ground ...
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... When used with internal T/R switch, this is a negative bi-directional RF port for the internal LNA and PA Modem RF input/output When used with internal T/R switch, this is a positive bi-directional RF port for the internal LNA and PA Not used May be grounded or left open MC13211/212/213 Technical Data, Rev. 1.8 Functionality Freescale Semiconductor ...
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... PTB2/AD1P2 Input/Output 55 PTB3/AD1P3 Input/Output 56 PTB4/AD1P4 Input/Output Freescale Semiconductor Description Modem power amplifier RF Open drain. Connect to VDDA through a bias output positive network when used with external balun. Not used when internal T/R switch is used. Modem power amplifier RF Open drain. Connect to VDDA through a bias output negative network when used with external balun ...
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... Normally factory test. Do not connect the RXTXEN input to the modem to enable CCA operations. MCU Port D Bit 3 drives Normally factory test. Do not connect the reset M_RST input to the modem. External package flag. Connect to ground. Common VSS MC13211/212/213 Technical Data, Rev. 1.8 Functionality Freescale Semiconductor ...
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... MISO is driven low when CE is negated. To use the MCU and modem signals as described programmed appropriately for the stated function. Freescale Semiconductor Table 3. Internal Functional Interconnects Modem GPIO2 output acts as “CRC Valid” status indicator for Stream Data Mode to MCU. ...
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... MCU SPI master MOSI output drives modem slave MOSI input Modem SPI slave MISO output drives MCU master MISO input MCU SPI master SS output drives modem slave CE input MC13211/212/213 Technical Data, Rev. 1.8 Figure 4 shows the SiP interconnections 11 RESET MCU Description Freescale Semiconductor ...
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... SPI protocol only uses data exchange in one direction at a time. The SPSCK signal is a clock output from the master and an input to the slave. The slave device must be selected by a low level on the slave select input (SS1 pin). Freescale Semiconductor MOS1 MOSI ...
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... Logic Packet Digital Processor Regulator H Cry stal Regulator VCO Receiv e RAM Regulator Arbiter Sequence Manager (Control Logic) IRQ Sy mbol Arbiter Arbiter Generation Freescale Semiconductor VDDA VBATT VDDINT VDDD VDDVCO RXTXEN CE MOSI MISO SPICLK ATTN RST GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 ...
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... If the 802.15.4 modem is in streaming mode, the MCU is notified by a recurring interrupt on a word-by-word basis. Figure 8 shows CCA reported power level versus input power. Note that CCA reported power saturates at about -57 dBm input power which is well above 802.15.4 Standard requirements. Freescale Semiconductor 1 byte 125 bytes maximum FLI Payload Data Figure 7 ...
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... Figure 9. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator 18 NOTE 802.15.4 Ac curac y and range Requirements -80 -70 -60 Input Pow er (dBm) 802.15.4 Accuracy and Range Requirements -75 -65 -55 -45 -35 MC13211/212/213 Technical Data, Rev. 1.8 -50 -25 -15 Freescale Semiconductor ...
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... Idle Mode through an internal timer comparator. Idle Crystal Reference Oscillator On with CLKO output available. SPI active. Receive Crystal Reference Oscillator On. Receiver On. Transmit Crystal Reference Oscillator On. Transmitter On. Freescale Semiconductor Table 5. Current drain in the various modes is listed in Definition MC13211/212/213 Technical Data, Rev. 1.8 Transition Time To or From Idle ...
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... SPI burst is shown in because the modem is limited by this number SPICLK Valid MISO MOSI Valid 20 NOTE Figure 10. The maximum SPI clock rate is 8 Mhz from the MCU SPI Burst Figure 10. SPI Single Burst Timing Diagram MC13211/212/213 Technical Data, Rev. 1 Freescale Semiconductor ...
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... After the final SPI burst negated to high to signal the end of the transaction. An example SPI read transaction with a 2-byte payload is shown in CE Clock Burst SPICLK MISO MOSI Freescale Semiconductor Valid Valid Header Read data Figure 11. SPI Read Transaction Diagram MC13211/212/213 Technical Data, Rev. 1.8 Figure 11 ...
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... The modem uses the 16 MHz crystal oscillator as the reference oscillator for the system and a programmable warp capability is provided controlled by programming CLKO_Ctl Register 0A, Bits 22 MC1321X 802.15.4 MODEM XTAL1 XTAL2 CLKO 16MHz Figure 12. Modem Crystal Oscillator MC13211/212/213 Technical Data, Rev. 1.8 Figure 12. Freescale Semiconductor ...
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... An external antenna switch is used to multiplex the antenna between receive and transmit. An LNA is in the receive path to add gain for greater receive sensitivity. Two external baluns are required to convert the single-ended antenna switch signals to the differential signals Freescale Semiconductor 50 100 ...
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... Figure 14. Using the MC1321x with External RF Components MC1321x 14B) Using External Antenna Switch With LNA L2 L3 RFIN_P (PAO_P) RFIN_M (PAO_M) VDDA Bypass Bypass L4 L5 CT_Bias PAO_P PAO_M 14C) Using Dual Antennae MC13211/212/213 Technical Data, Rev. 1 IN_ lun 1321x tl lun MC1321x Freescale Semiconductor ...
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... For lowest power operation, all unused I/O should be programmed as outputs during initialization. 2. Timer channels are limited as noted due to use of Port D I/O for internal signals. Figure 15. MCU Block Diagram (HCS08, Version A) Freescale Semiconductor INTERNAL BUS DEBUG MODULE (DBG) 8-BIT KEYBOARD INTERRUPT MODULE (KBI1) ...
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... The Stop2 Mode provides very low standby power consumption and maintains the contents of RAM and the current state of all of the I/O pins. Stop2 can be entered only if the LVD circuit is not enabled in Stop Modes (either LVDE or LVDSE not set). 26 NOTE MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor ...
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... Stop2. Instead they are maintained by virtue of the states of the internal logic driving the pins being maintained. Exit from Stop3 is performed by asserting RESET, an asynchronous interrupt pin, or through the real-time interrupt. The asynchronous interrupt pins are the IRQ or KBI pins. Freescale Semiconductor MC13211/212/213 Technical Data, Rev. 1.8 27 ...
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... RAM 4096 BYTES $107F $1080 FLASH 1920 BYTES $17FF $1800 HIGH PAGE REGISTERS $182B $182C FLASH 59348 BYTES $FFFF MC13213 28 $0000 DIRECT PAGE REGISTERS $007F $0080 RAM 2048 BYTES $087F $0880 UNIMPLEMENTED 3968 BYTES $17FF $1800 HIGH PAGE REGISTERS $182B ...
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... CLKO as external source, maximum FLL frequency is 32 MHz (16 MHz bus rate) with CLKO = 16 MHz or maximum FLL frequency is 40 MHz (20 MHz bus rate) with CLKO = 4 MHz. Freescale Semiconductor Figure 17, the ICG consists of four functional blocks. MC13211/212/213 Technical Data, Rev. 1.8 ...
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... The ICG’s FLL is used to generate frequencies that are programmable multiples of the external clock reference. — FLL engaged external unlocked is a transition state which occurs while the FLL is attempting to lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the target frequency. 30 MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor ...
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... Many instructions treat second general-purpose 8-bit register • Seven addressing modes: Freescale Semiconductor ICG SELECT ICGERCLK FREQUENCY DCO LOCKED REF LOOP (FLL) ...
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... INDEX REGISTER H:X H INDEX REGISTER (HIGH CONDITION CODE REGISTER ACCUMULATOR A INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 18. CPU Registers MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor ...
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... The MCU SPI port is used only in master mode on the MC1321x family. The user must program the SPI module for the proper characteristics as listed in the features below and also program the SS signal to have the proper use to support the modem transaction protocol for the modem CE signal. Freescale Semiconductor NOTE Figure 15) ...
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... EMPTY MASTER CLOCK SLAVE CLOCK LOGIC MOD- SSOE SPTEF SPRF SPTIE MODF SPIE MC13211/212/213 Technical Data, Rev. 1.8 PIN CONTROL M MOSI MOSI S M MISO MISO S MODEM SPI PORT M SPSCK SPICLK S MASTER/ SLAVE SS CE Connected onboard SiP SPI INTERRUPT REQUEST Freescale Semiconductor ...
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... KBI module. KBIP0 KBIPE0 KBIP3 KBIPE3 1 KBIP4 0 S KBIPE4 KBEDG4 1 KBIPn 0 S KBIPEn KBEDGn Freescale Semiconductor VDD CLR KEYBOARD INTERRUPT FF KBIMOD Figure 20. KBI Block Diagram MC13211/212/213 Technical Data, Rev. 1.8 BUSCLK KBACK RESET KBF SYNCHRONIZER STOP BYPASS ...
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... The TPM shares its I/O pins with general-purpose I/O port pins. Figure 21 one TPM, with various numbers of channels. 36 shows the structure of a TPM. Some MCUs include more than MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor ...
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... Double-buffered transmitter and receiver with separate enables • Programmable baud rates (13-bit modulo divider) • Interrupt-driven or polled operation: — Transmit data register empty and transmission complete Freescale Semiconductor CLOCK SOURCE SELECT OFF, BUS, XCLK, EXT CLKSB CLKSA COUNTER RESET ELS1B ...
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... The transmitter and receiver operate independently, although they use the same baud rate generator. During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes received data. Figure 22 38 and Figure 23 show the SCI transmitter and receiver block diagrams. MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor ...
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... INTERNAL BUS M 1 ¥ BAUD RATE CLOCK PE PT ENABLE TE TXDIR Freescale Semiconductor (WRITE-ONLY) SCID – Tx BUFFER 11-BIT TRANSMIT SHIFT REGISTER SHIFT DIRECTION T8 PARITY GENERATION TRANSMIT CONTROL SBK TDRE TIE TC TCIE Figure 22. SCI Transmitter MC13211/212/213 Technical Data, Rev. 1.8 LOOPS RSRC LOOP ...
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... PT 40 (READ-ONLY) SCID – Rx BUFFER DIVIDE 11-BIT RECEIVE SHIFT REGISTER WAKE WAKEUP LOGIC ILT RDRF RIE IDLE ILIE OR ORIE FE FEIE NF NEIE PARITY PF CHECKING PEIE Figure 23. SCI Receiver MC13211/212/213 Technical Data, Rev. 1 SHIFT DIRECTION RWU Rx INTERRUPT REQUEST ERROR INTERRUPT REQUEST Freescale Semiconductor ...
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... The module will continue to operate while the MCU is in wait mode and can provide a wake-up interrupt. Stop mode The IIC is inactive in Stop3 Mode for reduced power consumption. The STOP instruction does not affect IIC register states. Stop1 and Stop2 will reset the register contents. Freescale Semiconductor MC13211/212/213 Technical Data, Rev. 1.8 41 ...
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... IIC module. ADDRESS ADDR_DECODE CTRL_REG INPUT SYNC CLOCK CONTROL 42 FREQ_REG ADDR_REG STATUS_REG START STOP ARBITRATION CONTROL SDA SCL Figure 24. IIC Functional Block Diagram MC13211/212/213 Technical Data, Rev. 1.8 DATA BUS INTERRUPT DATA_MUX DATA_REG IN/OUT DATA SHIFT REGISTER ADDRESS COMPARE Freescale Semiconductor ...
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... Upon setting the ATDPU bit, the module is reactivated. During power-down mode, the ATD registers are still accessible. The reset state of the ATDPU bit is zero. Therefore, the module is reset into the power-down state. Freescale Semiconductor NOTE MC13211/212/213 Technical Data, Rev. 1.8 43 ...
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... DATA JUSTIFICATION CTL STATUS CONVERSION MODE CONTROL BLOCK POWERDOWN SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER (ATD) BLOCK = INTERNAL PINS = CHIP PADS Figure 25. ATD Block Diagram MC13211/212/213 Technical Data, Rev. 1.8 SAR_REG <9:0> RESULT REGISTERS CTL STATE MACHINE DIGITAL ANALOG CTL Freescale Semiconductor ...
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... Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information: — Change-of-flow addresses or — Event-only data • Two types of breakpoints: — Tag breakpoints for instruction opcodes — Force breakpoints for any address access • Nine trigger modes: Freescale Semiconductor MC13211/212/213 Technical Data, Rev. 1.8 45 ...
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... Table 6. LGA Package Maximum Ratings Symbol V BATT MC13211/212/213 Technical Data, Rev. 1 the programmable SS DD Value T 125 J T -55 to 125 stg , V -0.3 to 3.6 DDINT Vin -0 0.3) DDINT P 10 max I 120 DD ± Freescale Semiconductor Unit °C °C Vdc dBm mA mA ...
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... Crystal Reference Oscillator Frequency (±40 ppm over operating conditions to meet the 802.15.4 Standard the supply voltage is produced by a switching DC-DC converter, ripple should be less than 100 mV peak-to-peak. Freescale Semiconductor ) and negative (V ) clamp voltages, then use the larger of the two resistance values. SS and V ...
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... Max - 0.2 1.0 - 1.0 6 102 - 500 800 - ± 30% V DDINT 70 DDINT V DDINT 80 DDINT V DDINT 0 - 20% V DDINT Section 7.2, “Low Power Symbol Min Typ Max SENS - -92 - per - -92 -87 SENS - 10 - max - Freescale Semiconductor Unit µA µA µA µ µ Unit dBm dBm dBm ...
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... Measured with output power set to nominal (0 dBm) and temperature @ 25 °C L10 4.7nH U4 44 L11 GPIO1 39 4.7nH PAO_M 38 PAO_P 36 RFIN_P 35 L13 RFIN_M 34 CT_Bias 3.3nH MC1321x L14 3.3nH Freescale Semiconductor = 2 ° MHz, unless otherwise noted.) A ref = 2 ° MHz, unless otherwise noted.) A ref Symbol P out EVM VDDA Z4 C13 3 1 C17 2 5 10pF 1 ...
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... V — DD 0.85 × V — DD Freescale Semiconductor Unit ...
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... All functional non-supply pins are internally clamped Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Freescale Semiconductor (Temperature Range = –40 to 85°C Ambient) Symbol V ...
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... Freescale Semiconductor Temp. (° ...
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... Most customers are expected to find that auto-wake up from Stop2 or Stop3 can be used instead of the higher current wait mode. Wait mode typical is 560 μ and 422 μ with f 7 Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0), clock monitor disabled (LOCD = 1) Freescale Semiconductor (Temperature Range = –40 to 85°C Ambient) Symbol S3I MHz ...
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... MC13211/212/213 Technical Data, Rev. 1.8 Typical Max — 3.6 — 0.7 1.2 — 0.02 0.6 — — 100 — — 100 — — V SSAD — V DDAD — V DDAD — 200 300 — <0.01 0.02 – 0.3 — 0.3 DDAD Freescale Semiconductor Unit V mA μ μA V ...
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... Full-scale error is the difference between the transition to the last valid code and the ideal transition to that code. The ideal transition voltage to a given code is (Code–1/2)*(1/(V 10 Input leakage error is error due to input leakage across the real portion of the impedance of the network driving the analog pin. Reducing the impedance of the network reduces this error. Freescale Semiconductor Symbol Condition f 2.08V < V < ...
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... T IL ICG EXTAL R F Crystal or Resonator (See Note NOTE: Use fundamental mode crystal or ceramic resonator only. Figure 27. ICG Clock Basic Schematic Symbol Min MC13211/212/213 Technical Data, Rev. 1.8 XTAL Typ Max Unit 2 10 MΩ Ω 0 Freescale Semiconductor ...
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... Loss of DCO frequency 4, 5 Crystal start-up time Low range High range 4, 6 FLL lock time Low range High range FLL frequency unlock range FLL frequency lock range Freescale Semiconductor (max), Temperature Range = –40 to 85°C Ambient) DDA Symbol hi_byp f hi_eng f lo ...
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... MC13211/212/213 Technical Data, Rev. 1.8 Min Typical Max — 0.2 ± 0.5 ±2 — ±0.5 ±2 — percentage Jitter Min Typical Max dc — 20 700 1300 1.5 x — f Self_reset 34 x — f Self_reset 25 — 25 — 1 — cyc — 3 — 30 Freescale Semiconductor Unit % f ICG % . ICGOUT Unit MHz μ ...
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... In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V RESET PIN BKGD/MS Figure 29. Control Active Background Debug Mode Latch Timing Freescale Semiconductor and 80% V levels. Temperature range –40°C to 85° extrst Figure 28 ...
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... TPMext t 1.5 clkh t 1.5 clkl t 1.5 ICPW t Text t clkh t clkl Figure 31. Timer External Clock t ICPW t ICPW Figure 32. Timer Input Capture Pulse MC13211/212/213 Technical Data, Rev. 1.8 Max Unit f /4 MHz Bus — t cyc — t cyc — t cyc — t cyc Freescale Semiconductor ...
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... Data valid (after SCK edge) Master 8 Data hold time (outputs) Master 9 Rise time Input Output 10 Fall time Input Output 1 SS (OUTPUT) SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 5 MISO MSB IN (INPUT) 2 MOSI MSB OUT (OUTPUT) Freescale Semiconductor Table 20. SPI Timing Symbol SCK t Lead t Lag t WSCK ...
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... Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Non-volatile Memory. ...
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... The on-chip trim capability may be used to determine the closest standard value by adjusting the trim value via the SPI and observing the frequency at CLKO. Each internal trim load capacitor has a trim range of approximately steps. Initial tolerance for the internal trim capacitance is approximately ±15%. Freescale Semiconductor MC13211/212/213 Technical Data, Rev. 1.8 63 ...
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... Figure 34. MC1321x Modem Crystal Circuit Table 22. MC1321x Crystal Specifications Value Unit 16.000000 MHz 2 ± 10 ppm 3 ± 15 ppm ± 2 ppm Ω MC13211/212/213 Technical Data, Rev. 1.8 C10 6.8pF C11 6.8pF Table 22. A number of the stated 1 Condition at 25 °C Over desired temperature range max max Freescale Semiconductor ...
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... IRQ that signifies the modem is ready and in Idle mode; this can prevent a possible extraneous false interrupt request. – CLKO - is always an output. During Hibernate CLKO retains its output state, but does not toggle. During Doze, CLKO may toggle depending on whether it is being used. Freescale Semiconductor Value Unit <2 ...
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... Passive component values can vary as a function of circuit board layout as required to obtain best matching and RF performance GPIO1 39 PAO_M 38 1.5nH PAO_P 36 RFIN_P 35 L2 RFIN_M 34 3.9nH CT_Bias L4 MC1321x 1.5nH Figure 35. RF Single Port Application with an F-Antenna 66 NOTE LDB212G4005C-001 3.9nH 1.0pF C2 10pF MC13211/212/213 Technical Data, Rev. 1 Not Mounted ANT1 F_Antenna SMA_edge_Receptacle_Female 5 Freescale Semiconductor ...
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... The GPIO1 can only be used as a VDD source for a very low current load. L5 4.7nH GPIO1 39 4.7nH PAO_M 38 PAO_P 36 RFIN_P 35 L7 RFIN_M 34 CT_Bias 3.3nH MC1321x L9 3.3nH Figure 36. RF Dual Port Application with an F-Antenna Freescale Semiconductor NOTE VDDA 10pF 1.0pF 4 6 IC1 LDB212G4005C-001 3 OUT2 1 OUT1 C6 2 GND 10pF VCONT µ ...
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... Mechanical Diagrams Figure 37 and Figure 38 show the MC1321x mechanical information. 68 Figure 37. MC1321x Mechanical ( MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor ...
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... Freescale Semiconductor Figure 38. MC1321x Mechanical ( MC13211/212/213 Technical Data, Rev. 1.8 69 ...
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... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase ...