TRC104 RFM, TRC104 Datasheet
TRC104
Specifications of TRC104
Related parts for TRC104
TRC104 Summary of contents
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... The TRC104 includes a set of low-power states to reduce overall current consumption and extend battery life. The small size and low power requirements of the TRC104 make it ideal for a wide variety of short range radio applications. The TRC104 complies with Directive 2002/95/EC (RoHS). ...
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... Data Format Control ....................................................................................................................... 24 8.7 Preamble Control ............................................................................................................................ 25 8.8 Transmitter Rise/Fall Time Control ................................................................................................. 25 8.9 Address Length Control .................................................................................................................. 26 8.10 Destination Address...................................................................................................................... 26 8.11 Sender (Local Device) Address .................................................................................................... 27 8.12 Reserved....................................................................................................................................... 27 www.RFM.com E-mail: info@rfm.com ©2009 by RF Monolithics, Inc. Table of Contents Technical support +1.800.704.6079 Page TRC104 - 08/13/09 ...
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... Destination Address Written by Host, No Sender Address .......................................................... 32 10.3 Destination and Sender Addresses from Configuration Registers ............................................... 32 10.4 Destination Address Written by Host, Sender Address from Configuration Register................... 32 11 Package Dimensions.............................................................................................................................. 33 www.RFM.com E-mail: info@rfm.com ©2009 by RF Monolithics, Inc. Technical support +1.800.704.6079 Page TRC104 - 08/13/09 ...
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... External RF power input, 3.0 V typical IF ground Analog RSSI output - continuous mode only No connection - not used Transmit or receive complete interrupt output RSSI threshold interrupt output No connection - not used No connection - not used IC die pad on bottom of package - ground Table 1 Technical support +1.800.704.6079 Page TRC104 - 08/13/09 ...
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... MIN MAX +1.9 +3.6 -40 +85 O MIN TYP MAX UNITS 0.4 µA 1.4 µA µ 500 1500 mV -0.4 0.8 V 0.7*Vcc Vcc+0 µA 1 µA - 0.4 V Vcc-0 UNITS V °C dBm UNITS V °C = 25° 3 Test Conditions 16 MHz crystal Vcc Page TRC104 - 08/13/09 ...
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... MHz Test Conditions differential -3 10 BER -3 10 BER 1 MHz offset, unmodulated NRZ Test Condition differential programmable 1 Mb/s data rate, 0 dBm TX power 1 Mb/s data rate, 0 dBm TX power 0 dBm TX power 0 dBm TX power fixed for both data rates Page TRC104 - 08/13/09 ...
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... Test Condition 200 µs µs 200 ms 120 ms 120 ms 120 ms 1.5 µs 200 µs 200 µs 200 µs/step programmable 10/5 no external mV/µs 10 filter capacitor TYP MAX UNITS Test Condition 16 20 MHz µs 170 MHz from sleep mode 1.5 MHz 2527 TRC104 - 08/13/09 Page ...
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... Gaussian-filtered bit stream. 3.1 RF Port The TRC104 has a differential RF port that is capable of delivering the required transmitter output power at low supply voltages. The differential RF port also provides common mode signal rejection to enhance receiver interference immunity. A simple L-C balun can be used to convert the differential port to a single-ended output to drive an unbalanced antenna, as shown in Figure 3 ...
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... For Burst Transmit Mode, the TRC104 RF output ramp-up and ramp-down times are configurable, controlling excessive transmitter bandwidth due to fast rise and fall times of the transmitter RF envelope. After the PLL is locked for transmission, the power amplifier is ramped up stage by stage beginning with the lowest power level until the power level that is specified by the PWR bits in register 0x01 is reached ...
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... TRC104 will discard the current packet. 3.4 Crystal Oscillator At the 1 Mb/s RF data rate, the TRC104 uses a 16 MHz crystal. At the 250 kb/s RF data rate, the TRC104 can use any one of five standard crystal frequencies 12, 16 MHz. The crystal frequency is configured by setting the FXTAL bits in register 0x01. At the 250 kb/s data rate, the TRC104’s power consumption is reduced by using one of the lower crystal frequencies ...
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... The RSSI signal is an indication of received signal strength. A diagram of the RSSI implementation is shown in Figure 7. Once the RSSI signal is enabled by setting the RSSIA_rfsh bit of register 0x03 to 1, the TRC104 will begin to detect the strength of incoming signals. The RSSIA pin outputs an analog voltage corresponding to the strength of the received signal ...
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... The TRC104 can operate in one of five modes: Sleep, Stop, Stand-by, Configuration or Active TX/RX. Figure 8 details the state transitions between the operating modes. There are three input pins that determine the operating mode for the TRC104. The states of these pins are shown in Table 9 and associated timing diagrams are provided in the Sections below where needed. ...
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... No serial transaction can occur in Stop Mode. The typical turn-on time from Stop Mode is 1.5 ms. Any operation to the TRC104 must wait until the turn on period is complete. Figure 10 demonstrates the states of the mode control pins and the timing related to Stop Mode. ...
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... Figure 11and Table 10 show the timing for transmitting data on SDAT. Note that three 1 dummy bits must be sent prior to sending the preamble and the rest of the packet. The TRC104 should not be active for more than time to allow for internal auto-calibration. Typical calibration time is 200 µs. ...
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... Mode. Once the FIFO is loaded, three additional dummy bits (any value) are clocked in. The MODE pin is then de-asserted (low) and the packet transmission starts. At the end of the transmission the INT flag is asserted. The INT flag resets when the TRC104 is placed in another mode. Figure 13 and Table 12 show the serial port timing parameters for Burst Transmit Mode. ...
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... Section 5.2 are available for use in Burst Receive Mode. Using these features frees up the host microcontroller to perform other tasks packet is received, the TRC104 uses the preamble to lock to the incoming data rate and then determines if the packet is for it by testing the address following the preamble for a match to its own device address. If the addresses match, the TRC104 receives the remainder of the packet, including the sender address if present, the payload data and CRC ...
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... Configurable destination address • Configurable DC-balanced data scrambling/descrambling • Configurable CRC generation and error detection The configuration details of these features are covered below in Sections 6.1 through 6.4. Figure 15 shows the general format of a TRC104 packet. www.RFM.com E-mail: info@rfm.com ©2009 by RF Monolithics, Inc. Figure 14 ...
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... The transmit/receive FIFO length is set with the FIFO_len bits in configuration register 0X05. The length can be set from one to 32 bytes. The FIFO must be long enough to hold all payload data bytes. All TRC104 radios in a network must use the same FIFO length. The FIFO must be completely filled on every transmission. Padding bytes (user selected value) are used to fill up the transmit FIFO when payload data bytes do not completely fill it ...
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... DC-Balanced Scrambling The TRC104 is equipped with a scrambling/descrambling function to improve the DC-balance of a transmitted bit stream. The implementation is show in Figure 16. This function is enabled by setting the SCR_En bit in configuration register 0x02 to 1. The scrambling/descramble function is only available in Burst Packet Mode. 6.4 CRC Error Detection The CRC error detection option is enabled by setting the CRC_En bit in configuration register 0x02 to 1 ...
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... Two bytes are required for each configuration register transaction. The first byte contains the R/W bit (0 = read write) and the 7-bit configuration register address. The second byte contains the configuration value to be written or read from the address specified in the first byte. Figure 19 and Table 14 show the timing for a configuration read sequence from the TRC104. www.RFM.com E-mail: info@rfm.com © ...
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... Burst Transmit Mode, a FIFO write transaction is implemented on the serial interface. The CS pin must be held low during FIFO transactions. If the CS is allowed to go high, the TRC104 will interpret the data as a register configuration transaction and possibly corrupt the device configuration. See Sections 5.2.1 and 5.2.2 for details on Burst Transmit Mode and Burst Receive Mode using the FIFO ...
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... Reserved, always set to 000b Transmitter Output Power: 00 → -20 dBm 01 → -10 dBm r/w 10 → -5 dBm 11 → 0 dBm Crystal Frequency Selection: 000 → 4 MHz 001 → 8 MHz r/w 010 → 12 MHz 011 → 16 MHz 100 → 20 MHz Table 17 Technical support +1.800.704.6079 Page TRC104 - 08/13/09 ...
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... Analog RSSI refresh control bit (Continuous Mode only): 0 → Do not refresh RSSI value r/w 1 → Refresh RSSI value See Section 3.7 for details of RSSI operation DRSSI threshold: when the RSSIA level exceeds RSSIA_thr, the RSSID pin is set high r/w default is 0111b Table 19 Technical support +1.800.704.6079 Page TRC104 - 08/13/09 ...
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... Provided by the host microcontroller before data is written to FIFO FIFO length (number of payload data bytes, Burst Mode only): 00000 → 1 byte 00001 → 2 bytes … r/w 11111 → 32 bytes Payload data bytes = FIFO_len + 1 where 0 ≤ FIFO_len ≤ 31 default is 01111b Table 21 Technical support +1.800.704.6079 Page TRC104 - 08/13/09 ...
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... Power amplifier ramp-down time (Burst Mode only), reduces transmit bandwidth 00 → 5 µs 01 → 10 µs r/w 10 → 20 µs 11 → 30 µs Power amplifier turn-on delay time (Burst Mode only) 00 → 0 µs 01 → 50 µs r/w 10 → 100 µs 11 → 150 µs Table 23 Technical support +1.800.704.6079 Page TRC104 - 08/13/09 ...
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... Invalid, do not use default is 011b Table 24 R/W Description r/w Destination address 1 Table 25 R/W Description r/w Destination address 2 Table 26 R/W Description r/w Destination address 3 Table 27 R/W Description r/w Destination address 4 Table 28 R/W Description r/w Destination address 5 Table 29 Technical support +1.800.704.6079 Page TRC104 - 08/13/09 ...
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... Local device address 4 Table 33 R/W Description r/w Local device address 5 Table 34 R/W Description PLL pre start time: 0000000 → No pre turn-on time r/w PLL pre start time = PLL_ON * 20 µs, where 0 < PLL_ON < 255 Table 35 Technical support +1.800.704.6079 Page TRC104 - 08/13/09 ...
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... Do not write to configuration registers addresses 0x18 and higher, except as discussed in Section 8.18. 8.18 Default Overrides for Enhanced Performance TRC104 operation can be enhanced by overriding several default values in register addresses shown in Table 38. These override values should be written before the TRC104 is first placed in a transmit or receive mode. Register Address www.RFM.com E-mail: info@rfm ...
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... Configuration Example This example details the configuration of a TRC104 application with the following specifications: Radios in System Operating Frequency and Power RF Data Rate Address Length Base Address Remote Address Destination Address Sender Address Option Sender Address Output on Receive Payload Data Length DC-Balanced Data Scrambling ...
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... Following the 120 ms reset period and holding the control lines in Configuration Mode, write the Ch_8_RX configuration constant 0X8008 to the TRC104 (base or remote). Set the CS control line to 0 for at least 5 µs, and then set the CS control line back For the base TRC104, write the following additional configuration constants to the radio, cycling the CS control line to 0 for at least 5 µ ...
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... Ovr_39 → 0xB9B9 Ovr_4F → 0XCF66 Ovr_77 → 0XF75C 5. For the remote TRC104, write the following additional configuration constants to the radio, cycling the CS control line to 0 for at least 5 µs between each write: TX_Pwr → 0X811B FIFO_Sz → 0X8503 Pre_Ctl → 0X86B0 Addr_len → ...
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... All bytes have now been clocked from the FIFO. In this example, the two Sender address bytes and the four payload data bytes will be output. 9. Three more clock cycles must follow the final FIFO byte in order to reset the TRC104 to receive the next packet. The bits on these three clock cycles are discarded. ...
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... Table 40 Technical support +1.800.704.6079 Inches Min Nom Max 0.154 0.157 0.161 0.154 0.157 0.161 0.100 0.104 0.108 0.100 0.104 0.108 - 0.020 - - 0.100 - 0.014 0.016 0.022 0.007 0.009 0.011 0.028 0.030 0.031 0.008 0.008 0.008 0.000 0.001 0.002 Page TRC104 - 08/13/09 ...