SX1212IWLTRT Semtech, SX1212IWLTRT Datasheet
SX1212IWLTRT
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SX1212IWLTRT Summary of contents
Page 1
... EN 300-220 V2.1.1) and North American (FCC part 15.247 and 15.249) regulatory standards. Ordering Information Table 1: Ordering Information Part number Delivery SX1212IWLTRT Tape & Reel TQFN-32 package – Operating range [-40;+85°C] T refers to Lead Free packaging This device is WEEE and RoHS compliant Application Circuit Schematic Rev 2 – ...
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... POR .........................................................................72 7.4.2. Manual Reset ...........................................................72 7.5. Reference Design.............................................................73 7.5.1. Application Schematic..............................................73 7.5.2. PCB Layout ..............................................................73 7.5.3. Bill Of Material..........................................................74 8. Packaging Information ..............................................................75 8.1. Package Outline Drawing .................................................75 8.2. PCB Land Pattern.............................................................75 8.3. Tape & Reel Specification ................................................76 9. Revision History ........................................................................77 10. Contact Information.................................................................77 Page SX1212 www.semtech.com ...
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... Figure 54: POR Timing Diagram...................................................72 Figure 55: Manual Reset Timing Diagram ....................................72 Figure 56: Reference Design Circuit Schematic ...........................73 Figure 57: Reference Design‘s Stackup .......................................74 Figure 58: Reference Design Layout (top view)............................74 Figure 59: Package Outline Drawing ............................................75 Figure 60: PCB Land Pattern ........................................................75 Figure 61: Tape & Reel Dimensions .............................................76 Page SX1212 www.semtech.com ...
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... Phase-Locked Loop POR Power On Reset RBW Resolution BandWidth RF Radio Frequency RSSI Received Signal Strength Indicator Rx Receiver SAW Surface Acoustic Wave SPI Serial Peripheral Interface SR Shift Register Stby Standby Tx Transmitter uC Microcontroller VCO Voltage Controlled Oscillator XO Crystal Oscillator XOR eXclusive OR Page SX1212 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING This product datasheet contains a detailed description of the SX1212 performance and functionality. Please consult the Semtech website for the latest updates or errata. 1. General Description The SX1212 is a single chip FSK and OOK transceiver capable of operation in the 300 to 510MHz license free ISM frequency bands ...
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... ADVANCED COMMUNICATIONS & SENSING 1.2. Pin Diagram The following diagram shows the pins arrangement of the QFN package, top view. Notes: yyww refers to the date code ------ refers to the lot number Rev 2 – June 18th, 2009 SX1212 Figure 2: SX1212 Pin Diagram Page SX1212 www.semtech.com ...
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... NRZ data input and output (Continuous mode) O Interrupt output O Interrupt output O PLL lock detection output O No connect I/O Connect to GND VDD I Supply voltage O Regulated supply of the analog circuitry O Regulated supply of digital circuitry O Regulated supply of the PA I/O Connect to GND RFIO I/O RF input/output NC - Connect to GND Page SX1212 www.semtech.com ...
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... Crystal oscillator running Frequency synthesizer running Output power = +10 dBm (1) Output power = 1dBm Page SX1212 Min Max Unit -0.3 3.7 V -55 125 ° dBm Min Max Unit 2.1 3.6 V -40 +85 ° dBm Min Typ Max Unit - 0.1 2 µ µA - 1.3 1 3.0 3 www.semtech.com ...
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... Kb/s 50 200 kHz 12.8 15 MHz 2 - kHz 1 500 800 µs 180 - µs 200 - µs 250 - µs 260 - µs 290 - µs 320 - µs 340 - µs Typ Max Unit +12.5 - dBm -8.5 - dBm -112 - dBc/Hz - -47 dBc 120 500 µs 600 900 µs www.semtech.com ...
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... Ranging from sensitivity Page SX1212 Typ Max Unit - -104 - dBm - - - - - - - - - - -110 - dBm - - - - - - - - - - -12 - dBc - - - dBc - - - - - - - 250 kHz - 400 kHz - -28 - dBm - 280 500 µs - 600 900 µs - 400 - µs - 400 - µs - 460 - µs - 480 - µs - 520 - µs - 550 - µs - 600 - µ 1/Fdev www.semtech.com ...
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... NSS_DATA rising to falling edge. Note: on pin 10 (XTAL_P) and 11 (XTAL_N), maximum voltages of 1.8V can be applied. Rev 2 – June 18th, 2009 Conditions Min 0.8*VDD - Imax=1mA 0.9*VDD Imax=-1mA - - - 2 250 312 500 625 500 625 Page SX1212 Typ Max Unit - - V - 0.2*VDD 0.1*VDD MHz - 1 MHz - - µ www.semtech.com ...
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... Rev 2 – June 18th, 2009 I LO2 LO1 LO2 Tx Q RSSI LO2 Generator Figure 3: SX1212 Detailed Block Diagram Page SX1212 Waveform generator OOK IRQ_0 demod IRQ_1 BitSync MOSI Control MISO FSK SCK demod NSS_CONFIG NSS_DATA CLKOUT DATA TEST LO1 Rx PLL_LOCK LO2 Rx LO1 Tx LO2 Tx www.semtech.com ...
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... Biasing digital Biasing : blocks -VCO circuit -Ext. VCO tank VR_DIG VR_VCO Pin 28 Pin 3 220nF 100nF X7R X7R Figure 4: Power Supply Breakdown Page Reg_PA 1.80 V Biasing analog Biasing : blocks -PA Driver -PA choke (ext) VR_PA VR_1V Pin 29 Pin 27 1ųF 47nF Y5V X7R www.semtech.com SX1212 ...
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... Rev 2 – June 18th, 2009 ÷75.(P PFD ÷(R +1) i Fcomp LF_M XT_P Figure 5: Frequency Synthesizer Description ÷8 90° 90° ÷8 90° Figure 6: LO Generator Fcomp PLLBW ≤ 6 Page +1)+ Vtune LF_P VCO_P VCO_M VR_VCO LO1 Rx Receiver LOs I LO2 LO1 Tx Q Transmitter LOs I LO2 Tx Q www.semtech.com SX1212 ...
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... Note that an increase in inductance will result in an increase Vtune. Rev 2 – June 18th, 2009 350- 390- 430- 470- 390 430 470 510 010 011 100 101 ≤ ≤ 100 Vtune ( mV ) 200 Page SX1212 www.semtech.com ...
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... Due to the manner in which the baseband OOK symbols are generated, the signal is always offset by the FSK frequency deviation (Fdev - as programmed in MCParam_Freq_dev). Hence, the center of the transmitted OOK signal is: Rev 2 – June 18th, 2009 RL1 LF_M CL2 CL1 LF_P Figure 7: Loop Filter 9 = Frf , fsk Flo Fxtal ( = + Frf , fsk Page SX1212 ] ) + S www.semtech.com nd order ...
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... IF2. Note that from Section 3.4. recommended that IF2 be set to 100 kHz. Rev 2 – June 18th, 2009 9 = − Frf , ook , tx Flo Fdev Fxtal = + Frf , ook , − Frf , ook , rx Flo Fxtal ( = + Frf , ook , Page − S Fdev ] ) + − www.semtech.com SX1212 ...
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... Rev 2 – June 18th, 2009 Second First up-conversion up-conversion I LO2 LO1 LO2 Figure 8: Transmitter Architecture 1 Fdev Figure 9: I(t), Q(t) Overview ' = ⇒ + DATA ' ' 1 ' Frf Fdev = ⇒ − DATA ' ' ' ' 0 Frf Fdev Page SX1212 Interpolation DACs DDS filters Waveform generator Baseband I(t) Q(t) www.semtech.com Data Clock ...
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... Settings other than those programmable with a 12.8 MHz crystal can be obtained by selection of XTAL the correct reference oscillator frequency. Please contact your local Semtech representative for further details. 3.3.4. Fdev Setting in FSK Mode The frequency deviation, Fdev, of the FSK transmitter is programmed through bits MCParam_Freq_dev: For correct operation the modulation index ß ...
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... In OOK mode, the PA ramp times can be accurately controlled through the MCParam_PA_ramp register. Those bits directly control the slew rate of VR_PA output (pin 29). Table 11: PA Rise/Fall Times MCParam_PA_ramp t VR_PA 8 Rev 2 – June 18th, 2009 ⎡ BR ≅ Fdev ⎢ ⎣ (rise / fall) PA_OUT 2 Page SX1212 ⎤ ⎥ ⎦ www.semtech.com ...
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... Please refer to the reference design section for an optimized PA load setting. Rev 2 – June 18th, 2009 DATA VR_PA [ VR_PA VR_PA PA Output power PA_OUT PA_OUT Figure 10: PA Control Figure 11: Optimal Load Impedance Chart Page SX1212 Pmax-1dB circle Max Power Zopt = 30+j25 Ω www.semtech.com ...
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... In receive mode, both PA and PA regulator are off and VR_PA is tied to ground. The external inductance LT1 is then used to bias the LNA. Rev 2 – June 18th, 2009 VR_PA 47nF 100nH SAW PA RFIO Low-pass and DC block VR_PA Reg_PA Rx_on PA RFIO To LNA Figure 13: Front-end Description Page SX1212 Antenna port DC block www.semtech.com ...
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... Figure 15: FSK Receiver Setting First down-conversion IF1 LO2 Rx Figure 16: OOK Receiver Setting Page SX1212 OOK demod Control logic -Pattern recognition Bit -FIFO handler synchronizer -SPI interface -Packet handler FSK demod th of the RF frequency Image Frequencyl Channel LO1 Rx frequency Image Channel Frequency LO1 Rx frequency www.semtech.com ...
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... Fc BW ButterfFil t passive , filter Low-pass filter for FSK ( RXParam_PolyFilt_on=’’0’’ Polyphase filter for OOK ( RXParam_PolyFilt_on=’’1’’ ) the polyphase filter - Figure 17: Active Channel Filter Description Page ButterFilt f f requency C Canceled side of f requenc y www.semtech.com SX1212 ...
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... RXParam_ButterFilt. However, the whole receiver chain influences this cutoff frequency. Thus the channel select and resultant filter bandwidths are summarized in the following chart: Rev 2 – June 18th, 2009 ⎡ ⎤ Fdev ⎢ ⎣ ⎥ ⎦ FSK 2 > FSK drifts OOK Tbit = fo 100 kHz = RXParam _ PolypFilt " 0011 " − > OOK drifts Page SX1212 www.semtech.com ...
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... Butterworth Filter's BW, FSK 450 400 350 300 250 200 150 100 Val (RXParam_ButterFilt) [d] Figure 18: Butterworth Filter's Actual BW Polyphase Filter's BW, OOK 450 400 350 300 250 200 150 100 Val (RXParam_ButterFilt [d] RXParam_PolypFilt="0011" Figure 19: Polyphase Filter's Actual BW Page SX1212 Actual Theoretical Actual Theoretical www.semtech.com ...
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... IRQParam_Rx_stby_irq1. Figure 21 shows the timing diagram of the RSSI interrupt source, with IRQParam_RSSI_irq_thresh set to 28. Rev 2 – June 18th, 2009 RSSI Response -100 -80 -60 Pin [dBm] IF_Gain=00 IF_Gain=01 IF_Gain=10 Figure 20: RSSI Dynamic Range to the IRQ0 or IRQ1 Page -40 -20 0 IF_Gain=11 pins via bits IRQParam_Rx_stby_irq0 www.semtech.com SX1212 or ...
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... RXParam_OOK_thresh_type register. The recommended mode of operation is the “Peak” threshold mode, illustrated below in Figure 22: Rev 2 – June 18th, 2009 Clear interrupt Figure 21: RSSI IRQ Timings = 2 = Fdev IF 100 kHz = MCParam _ Freq _ dev " 00000011 2 * Fdev β = ≥ Page SX1212 " www.semtech.com ...
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... MCParam_OOK_floor_thresh. Rev 2 – June 18th, 2009 Zoom Zoom Decay defined in RXPAram_OOK_thresh_step Period as defined in RXParam_OOK_thresh_dec_period Figure 22: OOK Demodulator Description Page SX1212 ‘’Peak -6dB’’ Threshold ‘’Floor’’ threshold defined by MCParam_OOK_floor_thresh Noise floor of receiver Time Fixed 6dB difference www.semtech.com ...
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... Rev 2 – June 18th, 2009 Set SX1212 in OOK Rx mode Adjust Bit Rate, Channel filter BW Default RXParam_OOK_thresh setting No input signal Continuous Mode Monitor DATA pin (pin 20) Increment MCParam_OOK_floor_thres Glitch activity on DATA ? Optimization complete Figure 23: Floor Threshold Optimization Page SX1212 www.semtech.com ...
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... The BitSync is automatically activated in Buffered and Packet modes. The bit synchronizer bit-rate is controlled by MCParam_BR. For a given bit rate, this parameter is determined by: Rev 2 – June 18th, 2009 = ⇒ _ OOK _ cutoff 00 = ⇒ _ OOK _ cutoff 11 output DATA mode DCLK IRQ_1 Figure 24: BitSync Description F = XTAL MCParam Page Fcutoff π Fcutoff π www.semtech.com SX1212 ...
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... Bit Synchronizer and Active channel filter settings are a function of the reference oscillator crystal frequency, F Settings other than those programmable with a 12.8 MHz crystal can be obtained by selection of the correct reference oscillator frequency. Please contact your local Semtech representative for further details. 3.4.13. Data Output After OOK or FSK demodulation, the baseband signal is made available to the user on pin 20, DATA, when Continuous mode is selected ...
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... Input Input Input Input Input Input Input Input Input Input Input Input Input Output (1) Output Output Output (1) Output Output Input Output Input Output Output Output Page SX1212 Comment NSS_CONFIG has the priority over NSS_DATA Output only if NSS_CONFIG or NSSDATA=’0’ www.semtech.com ...
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... The uC processing overhead is hence reduced further compared to Buffered mode. The maximum payload length is limited to the maximum FIFO limit of 64 bytes Rev 2 – June 18th, 2009 SX1212 CONTROL PACKET FIFO HANDLER (+SR) Page SX1212 DATA IRQ_0 IRQ_1 SPI CONFIG NSS_DATA SCK DATA MOSI MISO www.semtech.com ...
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... As described below, only one interface can be selected at a time with NSS_CONFIG having the priority: Rev 2 – June 18th, 2009 Continuous Buffered Packet NSS_CONFIG MOSI SPI MISO CONFIG SCK (slave) SPI DATA (slave) NSS_DATA Page SX1212 NSS_CONFIG MOSI MISO SCK NSS_DATA µ C (master) www.semtech.com ...
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... Rev 2 – June 18th, 2009 SPI Interface Config Data Config None A(0) stop D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) Address = D(7) D(6) D(5) D(4) D(3) D(2) D(1) Figure 27: Write Register Sequence Page SX1212 New value at address A1 Current value at address A1* D(0) www.semtech.com HZ ...
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... A(0) stop Address = D(7) D(6) D(5) D(4) D(3) D(2) D(1) Figure 28: Read Register Sequence byte written D1(3) D1(2) D1(1) D1( Figure 29: Write Bytes Sequence (ex: 2 bytes) Page Current value at address byte written D2(7) D2(6) D2(5) D2(4) D2(3) D2(2) D2(1) D2( SX1212 www.semtech.com ...
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... Rev 2 – June 18th, 2009 byte read D1(4) D1(3) D1(2) D1(1) D1(0) HZ D2(7) D2(6) Figure 30: Read Bytes Sequence (ex: 2 bytes) byte1 byte0 8 SR (8bits) 1 MSB Figure 31: FIFO and Shift Register (SR) Page byte read D2(5) D2(4) D2(3) D2(2) D2(1) D2(0) FIFO LSB www.semtech.com SX1212 HZ ...
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... Rev 2 – June 18th, 2009 B+1 Figure 32: FIFO Threshold IRQ Source Behavior Comments In Buffered mode, FIFO cannot be written in Stby before Tx In Packet mode, FIFO can be written in Stby before Tx In Packet & Buffered modes FIFO can be read in Stby after Rx Page SX1212 # of bytes in FIFO www.semtech.com ...
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... The packet handler is the block used in Packet mode. Its functionality is fully described in section 5.5. 5.2.5. Control The control block configures and controls the full chip’s behavior according to the settings programmed in the configuration registers. Rev 2 – June 18th, 2009 Bit N-1 = Bit N = Sync_value[1] Sync_value[0] Figure 33: Sync Word Recognition Page SX1212 www.semtech.com ...
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... The use of DCLK is compulsory in FSK and optional in OOK. DATA (NRZ) DCLK Rev 2 – June 18th, 2009 SX1212 CONTROL Figure 34: Continuous Mode Conceptual View T_DATA T_DATA Figure 35: Tx Processing in Continuous Mode Page SX1212 DATA IRQ_0 IRQ_1(DCLK) SPI NSS_CONFIG CONFIG SCK MOSI MISO www.semtech.com ...
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... The tables below give the description of the interrupts available in Continuous mode. Table 17: Interrupt Mapping in Continuous Rx Mode Note: In Continuous mode, no interrupt is available in Stby mode Table 18: Interrupt Mapping in Continuous Tx Mode Rev 2 – June 18th, 2009 Figure 36: Rx Processing in Continuous Mode Rx_stby_irq_0 Rx 00 (d) Sync 01 RSSI IRQ_0 1x - DCLK IRQ_1 Tx - IRQ_0 DCLK IRQ_1 Page SX1212 www.semtech.com ...
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... SCK MOSI MISO Figure 37: uC Connections in Continuous Mode Description Defines data operation mode ( X Defines IRQ_0 source in Rx mode X Enables Sync word recognition X Defines Sync word size X Defines the error tolerance on Sync word recognition X Defines Sync word value Page SX1212 uC Continuous) www.semtech.com ...
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... Tx mode after waiting at least 1 bit period from the last bit processed by modulator. Rev 2 – June 18th, 2009 SX1212 CONTROL FIFO (+SR) Figure 38: Buffered Mode Conceptual View Page SX1212 IRQ_0 IRQ_1 SPI NSS_CONFIG CONFIG NSS_DATA SCK DATA MOSI MISO The Sync word recognition must be www.semtech.com ...
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... Figure 40 illustrates an Rx processing with a 16 bytes FIFO size and Fifo_fill_method=0. Please note that in the illustrative example of section 5.4.6, the uC does not retrieve any byte from the FIFO through SPI Data, causing overrun. Rev 2 – June 18th, 2009 from SPI Data Page b10 b11 b12 b13 b14 b15 www.semtech.com SX1212 XXX ...
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... Table 21: Interrupt Mapping in Tx Buffered Mode Rev 2 – June 18th, 2009 Sync ( Write_byte 10 /Fifoempty 11 Sync 00 ( Fifofull 10 RSSI 11 Fifo_threshold Tx_start_irq_0=0 (d) Fifo_threshold Tx_start_irq_0=1 /Fifoempty Tx_irq_1=0 (d) Fifofull Tx_irq_1=1 Tx_done Page SX1212 b10 b11 b12 b13 b14 b15 b14 b13 b12 b11 b10 Stby - - /Fifoempty - - Fifofull - Fifo_threshold Tx www.semtech.com b16 b15 ...
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... Defines IRQ_1 source in Rx & Stby modes X Defines IRQ_1 source in Tx mode X Defines FIFO filling method X Controls FIFO filling status X Defines Tx start condition and IRQ_0 source X Defines Sync word size X Defines the error tolerance on Sync word detection X Defines Sync word value Page SX1212 uC Description www.semtech.com ...
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... Wait for Fifo_threshold interrupt (i.e. Sync word has been detected and FIFO filled up to the defined threshold packet end Stby (SR’s content is lost). Read packet bytes from FIFO until /Fifoempty goes low (or correct number of bytes is read Sleep mode. Rev 2 – June 18th, 2009 Page SX1212 www.semtech.com ...
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... The length of the payload is set by the PKTParam_Payload_length register and is limited by the size of the FIFO selected. Rev 2 – June 18th, 2009 SX1212 CONTROL PACKET FIFO HANDLER (+SR) Figure 42: Packet Mode Conceptual View Page SX1212 IRQ_0 IRQ_1 SPI NSS_CONFIG CONFIG NSS_DATA SCK DATA MOSI MISO www.semtech.com ...
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... Optional Address byte (Node ID). Message data. Optional 2-bytes CRC checksum. Rev 2 – June 18th, 2009 Optional DC free data coding CRC checksum calculation Sync Word Address Message bytes byte 0 to (FIFO size) bytes Payload/FIFO Figure 43: Fixed Length Packet Format Page SX1212 CRC 2-bytes www.semtech.com ...
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... Payload_ready and CRC_OK interrupts (the latter only if CRC is enabled) can be generated to indicate the end of the packet reception. Rev 2 – June 18th, 2009 Optional DC free data coding CRC checksum calculation Sync Word Length Address Message 0 to (FIFO size - 1) bytes bytes byte byte Payload/FIFO Figure 44: Variable Length Packet Format Page SX1212 CRC 2-bytes www.semtech.com ...
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... In variable length Packet mode, PKTParam_Payload_length must be programmed with the maximum length permitted. If received length byte is smaller than this maximum then the packet is accepted and processed, otherwise it is discarded. Rev 2 – June 18th, 2009 can also be fully or partially Page SX1212 retrieved in Stby mode via www.semtech.com ...
Page 53
... The NRZ data is converted to Manchester code by coding ‘1’ as “10” and ‘0’ as “01”. In this case, the maximum chip rate is the maximum bit rate given in the specifications section and the actual bit rate is half the chip rate. Rev 2 – June 18th, 2009 CRC Polynomial = Figure 45: CRC Implementation Page www.semtech.com SX1212 0 X ...
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... Payload whitening/de-whitening is thus made transparent for the user, who still provides/retrieves NRZ data to/from the FIFO 5.5.7. Interrupt Signal Mapping Tables below give the description of the interrupts available in Packet mode. Rev 2 – June 18th, 2009 1/BR ...Sync Figure 46: Manchester Encoding/Decoding Figure 47: Data Whitening Page Payload... ite www.semtech.com SX1212 ... t ... ... 0 X ...
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... Rev 2 – June 18th, 2009 Rx 00 (d) Payload_ready 01 Write_byte 10 /Fifoempty 11 Sync or Adrs_match* 00 (d) CRC_OK 01 Fifofull 10 RSSI 11 Fifo_threshold Tx_start_irq_0=0 (d) Fifo_threshold Tx_start_irq_0=1 /Fifoempty Tx_irq_1=0 (d) Fifofull Tx_irq_1=1 Tx_done SX1212 IRQ_0 IRQ_1 NSS_CONFIG NSS_DATA SCK MOSI MISO Figure 48: uC Connections in Packet Mode Page SX1212 Stby - - /Fifoempty - - Fifofull - Fifo_threshold Tx uC www.semtech.com ...
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... Defines node address for Rx address filtering X X Defines packet format (fixed or variable length) X Defines the size of preamble to be transmitted X X Enables whitening/de-whitening process X X Enables CRC calculation/check X Enables and defines address filtering X Enables FIFO autoclear if CRC failed X X Defines FIFO access in Stby mode Page SX1212 www.semtech.com ...
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... FIFO. If the payload is read in Stby mode, then CRC_status is cleared when the user goes back to Rx mode and a new Sync word is detected. The Fifo_fill_method and Fifo_fill bits don’t have any meaning in the Packet mode and should be set to their default values only. Rev 2 – June 18th, 2009 Page SX1212 www.semtech.com ...
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... Data operation mode: 00 -> continuous mode (d) r/w 01 -> buffered mode 1X -> packet handling mode RxTx modulation scheme: 00 -> Reset r/w 01 -> OOK 10 -> FSK (d) 11 -> Direct mode of transmitter (internal). Reserved (external) Page SX1212 www.semtech.com ...
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... S counter, active when RPS_select=”1” r/w (d): 19h; default values of R2, P2, S2 generate 435.0 MHz in FSK mode Reserved r/w (d):”000” Page SX1212 , 0 ≤ C ≤ 255, where C is the value in the register ≤ D ≤ 255, where D is the value in the register. www.semtech.com ...
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... Standby mode (Cf sections 5.4.4 and 5.5.7) Tx start condition and IRQ_0 source: 0 Start transmission when the number of bytes in FIFO is greater than or r/w equal to the threshold set by MCParam_Fifo_thresh parameter (Cf section 5.2.2.3), IRQ_0 mapped to Fifo_threshold ( starts if FIFO is not empty, IRQ_0 mapped to /Fifoempty Page SX1212 www.semtech.com ...
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... Writing ‘1’ clears the bit PLL status: r/w/ 0 not locked c 1 locked Writing a ‘1’ clears the bit PLL_lock detect flag mapped to pin 23: r/w 0 Lock detect disabled, pin Lock detect enabled(d) RSSI threshold for interrupt (coded as RSSI) (d): “00000000” Page SX1212 www.semtech.com ...
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... Sync word recognition: r/w 0 off ( Sync word size bits r bits 10 24 bits 11 32 bits (d) Number of errors tolerated in the Sync word recognition error (d) r error 10 2 errors 11 3 errors Reserved r/w (d):”0” Page SX1212 + 1 Val ( ButterFilt ) . 8 ( PolypFilt _ center ) 8 www.semtech.com ...
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... BR / 32.π Description st r/w 1 Byte of Sync word (d): “00000000” Byte of Sync word (only used if Sync_size ≠ 00) (d): “00000000” Byte of Sync word (only used if Sync_size = 1x) (d): “00000000” Byte of Sync word (only used if Sync_size = 11) (d): “00000000” Page SX1212 www.semtech.com ...
Page 64
... RW Description r/w Clkout control 0 Disabled 1 Enabled, Clk frequency set by Clkout_freq (d) r/w Frequency of the signal provided on CLKOUT: fclkout = if Clkout_freq = “00000” f xtal f = xtal fclkout 2 ⋅ Clkout _ freq (d): 01111 (= 427 kHz) r/w Reserved (d): “00” Page SX1212 Val ( InterpFilt otherwise www.semtech.com ...
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... Node_adrs & 0x00 & 0xFF accepted, else rejected. r CRC check result for current packet (READ ONLY): 0 Fail 1 Pass r/w FIFO auto clear if CRC failed for current packet (d) 1 off r/w FIFO access in standby mode: 0 Write (d) 1 Read r/w Reserved (d): “000000” Page SX1212 www.semtech.com ...
Page 66
... GUI To aid the user with calculating appropriate R, P and S values, software is available to perform the frequency calculation. The SX1212 PLL frequency Calculator Software can be downloaded from the Semtech website. 7.2.2. .dll for Automatic Production Bench The Dynamically Linked Library (DLL) used by the software to perform these calculations is also provided, free of charge, to users, for inclusion in automatic production testing ...
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... Receiver is ready : -RSSI sampling is valid after a 1/Fdev period -Received data is valid Wait TS FS Set SX1212 in Rx mode Wait for Receiver settling Set SX1212 in FS mode Wait for PLL settling Figure 49: Optimized Rx Cycle Page SX1212 Time SX1212 can be put in Any other mode www.semtech.com ...
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... TS TR Data transmission can start in Continuous and Buffered modes Wait TS FS Set SX1212 in Tx mode Packet mode starts its operation Set SX1212 in FS mode Wait for PLL settling Figure 50: Optimized Tx Cycle Page SX1212 Time SX1212 can be put in Any other mode www.semtech.com ...
Page 69
... IDDFS 1.3mA typ. Wait TS TR Wait TS HOP 1. Set R2/P2/S2 2. Set SX1212 in FS mode, change MCParam_Band if needed, then switch from R1/P1/S1 to R2/P2/S2 Figure 51: Tx Hop Cycle Page SX1212 Time SX1212 is now ready for data transmission Set SX1212 back in Tx mode www.semtech.com ...
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... IDDFS 1.3mA typ. Wait TS RE SX1212 is now ready for data reception Wait TS HOP 1. Set R2/P2/S2 2. Set SX1212 in FS mode, change MCParam_Band if needed, then switch from R1/P1/S1 to R2/P2/S2 Figure 52: Rx Hop Cycle Page SX1212 Time Set SX1212 back in Rx mode www.semtech.com ...
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... SX1212 mode Rev 2 – June 18th, 2009 IDD IDDT IDDR Wait TS TR SX1212 is now ready for data transmission Set SX1212 in Tx mode Figure 53 Cycle Page Wait TS RE SX1212 is ready to receive data Set SX1212 in Rx mode www.semtech.com SX1212 Time ...
Page 72
... VDD. Rev 2 – June 18th, 2009 Undefined Wait for Chip is ready from 10 ms this point on Figure 54: POR Timing Diagram Wait for > 100 High-Z ’’1’’ High-Z Figure 55: Manual Reset Timing Diagram Page SX1212 Chip is ready from this point on www.semtech.com ...
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... PCBs standard PCB technology (2 layers, 1.6mm, std via & clearance) => low cost Its performance is quasi-insensitive to dielectric thickness => minimal design effort to transfer to other PCB technologies (thickness layers, etc...) Rev 2 – June 18th, 2009 Figure 56: Reference Design Circuit Schematic Page SX1212 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING The layers description is illustrated in Figure 57: The layout itself is illustrated in Figure 58. Please contact Semtech for Gerber files. 9mm 7.5.3. Bill Of Material Table 35: Reference Design BOM Ref Value 330MHz 434MHz U1 SX1212 U2 330 MHz 434 MHz Q1 12.8 MHz L1 C10, C11 C12* *Not part of the ref ...
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... BSC 0.50 BSC .012 .016 .020 0.30 0.40 0. .003 0.08 .004 0.10 DIMENSIONS INCHES MILLIMETERS (.197) (5.00) .165 4.20 .146 3.70 .146 3.70 .020 0.50 .012 0.30 .031 0.80 .228 5.80 SX1212 www.semtech.com ...
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... Rev 2 – June 18th, 2009 Direction of Feed Reel Reel Reel Ao/Bo Ko Size Width 5.25 1.10 330.2 12.4 +/-0.2 +/-0.1 Figure 61: Tape & Reel Dimensions Page SX1212 Min. Min.Trail QTY per Leader er Length Reel Length 400 400 3000 www.semtech.com ...
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... OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless a gainst all claims, costs damages and attorney fees which could arise. ...