IC SOC W/RF TXRX 8051 MCU 36-QFN

CC2511F32RSP

Manufacturer Part NumberCC2511F32RSP
DescriptionIC SOC W/RF TXRX 8051 MCU 36-QFN
ManufacturerTexas Instruments
SeriesCC2511
CC2511F32RSP datasheet
 


Specifications of CC2511F32RSP

Frequency2.4GHzData Rate - Maximum500kBaud
Modulation Or ProtocolISM, SRDApplicationsConsumer Electronics, Wireless Input Devices
Power - Output1dBmSensitivity-103dBm
Voltage - Supply2 V ~ 3.6 VCurrent - Receiving17.1mA
Current - Transmitting16mAData InterfacePCB, Surface Mount
Memory Size32kB Flash, 4kB RAMAntenna ConnectorPCB, Surface Mount
Package / Case36-QFNWireless Frequency2400 MHz to 2483.5 MHz
Operating Supply Voltage3.3 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature0 C
Frequency Range2400MHz To 2483.5MHzData Rate500Kbps
Receiving Current17.1mATransmitting Current16mA
Rf Ic Case StyleQFNNo. Of Pins36
Supply Voltage Range3V To 3.6VRohs CompliantYes
For Use With296-23155 - KIT EVAL MODULE FOR CC2511CC2510-CC2511DK - KIT DEV FOR CC2510/CC2511Lead Free Status / RoHS StatusLead free / RoHS Compliant
Operating Temperature-Other names296-25933
CC2511F32RSP
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Page 1/244

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Low-Power SoC (System-on-Chip) with MCU, Memory,
2.4 GHz RF Transceiver, and USB Controller
Applications
• 2400 -
2483.5
MHz ISM/SRD
systems
• Consumer electronics
• Wireless keyboard and mouse
• Wireless voice-quality audio
Product Description
CC2510Fx/CC2511Fx
The
is a true low-cost 2.4
GHz system-on-chip (SoC) designed for low-
power
wireless
applications.
CC2510Fx/CC2511Fx
combines the excellent
performance
of
the
state-of-the-art
CC2500
transceiver
with an industry-standard
enhanced 8051 MCU, up to 32 kB of in-system
programmable flash memory and 4 kB of
RAM, and many other powerful features. The
small 6x6 mm package makes it very suited
for applications with size limitations.
CC2510Fx/CC2511Fx
The
is highly suited for
systems where very low power consumption is
required. This is ensured by several advanced
low-power operating modes. The
adds a full-speed USB controller to the feature
CC2510Fx
set of the
. Interfacing to a PC using
the USB interface is quick and easy, and the
high data rate (12 Mbps) of the USB interface
avoids the bottlenecks of RS-232 or low-speed
USB interfaces.
Key Features
• Radio
o High-performance RF transceiver based on
the market-leading CC2500
o Excellent receiver selectivity and blocking
performance
o High sensitivity (−103 dBm at 2.4 kBaud)
o Programmable data rate up to 500 kBaud
o Programmable output power up to 1 dBm for
all supported frequencies
o Frequency range: 2400 - 2483.5 MHz
o Digital RSSI / LQI support
• Current Consumption
o Low current consumption (RX: 17.1 mA @
2.4 kBaud, TX: 16 mA @ −6 dBm output
power)
o 0.3 µA in PM3 (the operating mode with the
lowest power consumption)
CC2510Fx / CC2511Fx
• RF enabled remote controls
band
• Wireless sports and leisure equipment
• Low power telemetry
CC2511Fx
: USB dongles
The
RF
CC2511Fx
• MCU, Memory, and Peripherals
o High performance and low power 8051
microcontroller core.
o 8/16/32 kB in-system programmable flash,
and 1/2/4 kB RAM
o Full-Speed USB Controller with 1 kB USB
CC2511Fx
FIFO (
2
o I
S interface
o 7 - 12 bit ADC with up to eight inputs
o 128-bit AES security coprocessor
o Powerful DMA functionality
o Two USARTs
o 16-bit timer with DSM mode
o Three 8-bit timers
o Hardware debug support
CC2510Fx
o 21 (
• General
o Wide supply voltage range (2.0V - 3.6V)
o Green package: RoHS compliant and no
antimony or bromine, 6x6mm QFN 36
SWRS055F
)
CC2511Fx
) or 19 (
) GPIO pins
Page 1 of 241

CC2511F32RSP Summary of contents

  • Page 1

    Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller Applications • 2400 - 2483.5 MHz ISM/SRD systems • Consumer electronics • Wireless keyboard and mouse • Wireless voice-quality audio Product Description CC2510Fx/CC2511Fx The is a true ...

  • Page 2

    Table of Contents ABBREVIATIONS................................................................................................................................................ 4 1 REGISTER CONVENTIONS .................................................................................................................. 5 2 KEY FEATURES (IN MORE DETAILS) .............................................................................................. 6 2 IGH ERFORMANCE AND 2.2 8/16/ VOLATILE 2 USB C ULL PEED ...

  • Page 3

    D C .................................................................................................................................... 69 EBUG OMMANDS 12 PERIPHERALS....................................................................................................................................... 73 12 OWER ANAGEMENT AND 12.2 R ......................................................................................................................................................... 80 ESET 12 .................................................................................................................................. 81 LASH ONTROLLER 12.4 I/O P ................................................................................................................................................... 87 ORTS 12.5 DMA C ................................................................................................................................... 98 ONTROLLER ...

  • Page 4

    Abbreviations ∆Σ Delta-Sigma ADC Analog to Digital Converter AES Advanced Encryption Standard AGC Automatic Gain Control ARIB Association of Radio Industries and Businesses BCD Binary Coded Decimal BER Bit Error Rate BOD Brown Out Detector CBC Cipher Block Chaining CBC- ...

  • Page 5

    Register Conventions Each SFR is described in a separate table. The table heading is given in the following format: REGISTER NAME (SFR Address) - Register Description. Each RF register is described in a separate table. The table heading is ...

  • Page 6

    Key Features (in more details) 2.1 High-Performance and 8051-Compatible Microcontroller • Optimized 8051 core which typically gives 8x the performance of a standard 8051 • Two data pointers • In-circuit interactive supported by the IAR Workbench through a simple ...

  • Page 7

    The high speed crystal oscillator must be used when the radio is active. • Clock source for ultra-low operation can be either a low-power RC oscillator or an optional 32.768 kHz crystal oscillator • Very fast transition to active mode ...

  • Page 8

    Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 2 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Parameter Supply voltage (VDD) Voltage on ...

  • Page 9

    Operating Conditions CC2510Fx 4.1 Operating Conditions CC2510Fx The operating conditions for Parameter Operating ambient temperature Operating supply voltage (VDD) Table 3: Operating Conditions for CC2511Fx 4.2 Operating Conditions CC2511Fx The operating conditions for Parameter Operating ambient temperature, ...

  • Page 10

    Electrical Specifications 6.1 Current Consumption T = 25°C, VDD = 3 nothing else stated. All measurement results are obtained using the A CC2510EM reference design ([1]). Parameter Min Typ Max Active mode, full 4.8 speed (high speed ...

  • Page 11

    Parameter Min Typ Max 19.4 15.7 16.9 Active mode with radio 18.5 15.5 26 PM0 4.3 PM1 220 PM2 0.5 PM3 0.3 Peripheral Current Consumption Timer 1 2.7 Timer 2 1.3 Timer 3 1.6 Timer 4 2 ...

  • Page 12

    Current Consumption Active Mode. No Peripherals Running. 6,0 5,0 4,0 3,0 2,0 1,0 0 Measurements done for all valid CLKCON.CLKSPD settings (000 – 111 for HS XOSC, 001 – 111 for HS RCOSC) Figure 1: ...

  • Page 13

    RF Receive Section T = 25°C, VDD = 3 nothing else stated. All measurement results are obtained using the A CC2510EM reference design ([1]). Parameter Min Typ Max Digital channel 58 812 filter bandwidth 2.4 kBaud data ...

  • Page 14

    Parameter Min Typ Max 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth) Receiver −90 sensitivity Saturation −11 Adjacent 21 channel rejection Alternate 30 channel rejection Blocking ...

  • Page 15

    RF Transmit Section T = 25°C, VDD = 3 nothing else stated. All measurement results are obtained using the A CC2510EM reference designs ([1]). Parameter Min Typ Differential load 80 + j74 impedance Output power, highest setting ...

  • Page 16

    Crystal Oscillators CC2510Fx 6.4.1 Crystal Oscillator T = 25°C, VDD = 3 nothing else is stated. A Parameter Min Typ Crystal frequency 24 26 Crystal frequency ±40 accuracy requirement Load capacitance 10 13 ...

  • Page 17

    Crystal Oscillator T = 25°C, VDD = 3.0V if nothing else is stated. A Parameter Min Crystal frequency C 0 Load capacitance ESR Start-up time Table 13: 32.768 kHz Crystal Oscillator Parameters 6.6 Low Power RC Oscillator ...

  • Page 18

    High Speed RC Oscillator T = 25°C, VDD = 3 nothing else is stated. A Parameter Min 2 Calibrated frequency 12 Uncalibrated frequency accuracy Calibrated frequency accuracy Start-up time Temperature coefficient Supply voltage coefficient Calibration time Table ...

  • Page 19

    Parameter Min 4 PLL turn-on / hop time 72.4 81 switch 29.0 32 switch 30.0 33.6 4 PLL calibration time 707 796 Table 16: Frequency Synthesizer Parameters 6.9 Analog Temperature Sensor T ...

  • Page 20

    ADC T = 25°C, VDD = 3.0V if nothing else stated. The numbers given here are based on tests performed A in accordance with IEEE Std 1241-2000 [7]. The ADC data are from CC2510x/C2511Fx uses ...

  • Page 21

    Parameter Min Typ 5 SINAD 35.4 Single ended input 46.8 (−THD+N) 57.5 66.6 5 SINAD 40.7 Differential input 51.6 (−THD+N) 61.8 70.8 Conversion time 132 Current consumption 1.2 Table 18 bit ADC Characteristics Max ...

  • Page 22

    Control AC Characteristics T = 25°C, VDD = 3 nothing else stated. All measurement results are obtained using the A CC2510EM reference designs ([1]). Parameter Min Typ System clock, f SYSCLK SYSCLK SYSCLK ...

  • Page 23

    Filtering of RESET_N pin The RESET_N pin is sensitive to noise and can cause unintended reset of the chip. For a long reset line add an external RC filter with values 1 nF and 2.7 kΩ close to the ...

  • Page 24

    Debug Interface AC Characteristics T = 25°C, VDD = 3 nothing else stated. All measurement results are obtained using the A CC2510EM reference designs ([1]). Parameter Min Debug clock period 125 Debug data setup 5 Debug data ...

  • Page 25

    Timer Inputs AC Characteristics T = 25°C, VDD = 3 nothing else stated. All measurement results are obtained using the A CC2510EM reference designs ([1]). Parameter Input capture pulse width Table 23: Timer Inputs AC Characteristics 6.16 ...

  • Page 26

    Pin and I/O Port Configuration CC2510Fx The pin-out is shown in Figure 7 and Table 25. See Section 12.4 for details on the I/O configuration. 1 P1_2 2 DVDD P1_1 3 4 P1_0 5 P0_0 6 P0_1 7 P0_2 ...

  • Page 27

    Pin Pin Name Pin Type - AGND Ground 1 P1_2 D I/O 2 DVDD Power (Digital) 3 P1_1 D I/O 4 P1_0 D I/O 5 P0_0 D I/O 6 P0_1 D I/O 7 P0_2 D I/O 8 P0_3 D I/O ...

  • Page 28

    CC2511Fx The pin-out is shown in Figure 8 and Table 26. See Section 12.4 for details on the I/O configuration. 1 P1_2 2 DVDD P1_1 3 4 P1_0 5 P0_0 6 P0_1 P0_2 7 P0_3 8 P0_4 9 Note: The ...

  • Page 29

    Pin Pin Name Pin Type - AGND Ground 1 P1_2 D I/O 2 DVDD Power (Digital) 3 P1_1 D I/O 4 P1_0 D I/O 5 P0_0 D I/O 6 P0_1 D I/O 7 P0_2 D I/O 8 P0_3 D I/O ...

  • Page 30

    Circuit Description RESET_N RESET XOSC_Q2 HIGH SPEED CRYSTAL OSC XOSC_Q1 (24 – 27 MHz) P2_4 32.768 kHz CRYSTAL OSC P2_3 P2_2 HIGH SPEED DEBUG P2_1 INTERFACE P2_0 P1_7 8051 CPU P1_6 CORE P1_5 P1_4 P1_3 P1_2 DMA P1_1 P1_0 ...

  • Page 31

    CPU and Peripherals The 8051 CPU core is a single-cycle 8051- compatible core. It has three different memory access buses (SFR, CODE/XDATA), a debug interface, and an extended interrupt unit servicing 18 interrupt sources. See Section 10 for details ...

  • Page 32

    In the latter case, each pin can be configured as an input or output and it is also possible to configure the input mode to be pull- up, pull-down, or tristate. ...

  • Page 33

    Radio CC2510Fx/CC2511Fx features an RF transceiver based on the industry-leading 9 Application Circuit Only a few external components are required CC2510Fx/CC2511Fx for using the recommended application circuit for is shown in Figure 10. The recommended CC2511Fx application circuits for ...

  • Page 34

    C181 and C171. This crystal can be used by the Sleep Timer if more accurate wake-up intervals are needed than what the internal RC oscillator can provide. When not using X2, P2_3 and P2_4 may be used ...

  • Page 35

    Figure 10: Application Circuit for Figure 11: Application Circuit for CC2510Fx (excluding supply decoupling capacitors) CC2511Fx with Fundamental Crystal (excluding supply decoupling capacitors) SWRS055F Page 35 of 241 ...

  • Page 36

    Figure 12: Application Circuit for CC2511Fx rd with 3 Overtone Crystal (excluding supply decoupling capacitors) SWRS055F Page 36 of 241 ...

  • Page 37

    Component Description C301 Decoupling capacitor for on-chip voltage regulator to digital part C203/C214 Crystal loading capacitors (X3) C202/C212/C213 Crystal loading capacitors (X4) C201/C211 Crystal loading capacitors (X1) C231/C241 RF balun DC blocking capacitors C232/C242 RF balun/matching capacitors C233/C234 RF LC ...

  • Page 38

    Component Value C301 1 µF ± 10%, 0402 X5R C203/C214 33 pF ± 5%, 0402 NP0 C202 56 pF C212 10 nF C213 33 pF C201/C211 27 pF ± 5%, 0402 NP0 C231, C241 100 pF ± 5%, 0402 NP0 ...

  • Page 39

    Figure 13: Left: Top Solder Resist Mask (negative). Right: Top Paste Mask. Circles are Vias. 10 8051 CPU This section describes the 8051 CPU core, with interrupts, memory, and instruction set. 10.1 8051 Introduction CC2510Fx/CC2511Fx The includes an 8-bit CPU ...

  • Page 40

    SFR. A 7-bit read/write register memory space, which can be directly accessed by a single CPU instruction. For SFRs whose address is divisible by eight, each bit is also individually addressable. The four different memory spaces are distinct in the ...

  • Page 41

    CC2510F16 CC2511F16 Figure 15: / SWRS055F Memory Mapping Page 41 of 241 ...

  • Page 42

    Figure 16: Details about the mapping of all 8051 memory spaces are given in the next section. 10.2.2 8051 Memory Space This section describes the details of each standard 8051 memory space. Any differences between the standard CC2510Fx/CC2511Fx is described. ...

  • Page 43

    All SFR except the registers shown in gray in Table 30 are mapped into address range 0xDF80 - 0xDFFF. • The USB registers are mapped into the address range 0xDE00 - 0xDE3F on the CC2511Fx , but are not ...

  • Page 44

    Information Page (1 KB) which contains the Flash Lock Bits. The lock protect bits are written as a normal flash write to FWDATA but the Debug Interface needs to select the Flash Information Page first instead of the Flash Main ...

  • Page 45

    Register SFR Module Name Address ADCCON1 0xB4 ADC ADCCON2 0xB5 ADC ADCCON3 0xB6 ADC ADCL 0xBA ADC ADCH 0xBB ADC RNDL 0xBC ADC RNDH 0xBD ADC ENCDI 0xB1 AES ENCDO 0xB2 AES ENCCS 0xB3 AES DMAIRQ 0xD1 DMA DMA1CFGL 0xD2 ...

  • Page 46

    Register SFR Module Name Address CLKCON 0xC6 PMC RFIM 0x91 RF RFD 0xD9 RF RFIF 0xE9 RF RFST 0xE1 RF WORIRQ 0xA1 Sleep Timer WORCTRL 0xA2 Sleep Timer WOREVT0 0xA3 Sleep Timer WOREVT1 0xA5 Sleep Timer WORTIME0 0xA4 Sleep Timer ...

  • Page 47

    Register SFR Module Name Address U0GCR 0xC5 USART0 U1CSR 0xF8 USART1 U1DBUF 0xF9 USART1 U1BAUD 0xFA USART1 U1UCR 0xFB USART1 U1GCR 0xFC USART1 ENDIAN 0x95 MEMORY WDCTL 0xC9 WDT Table 31: CC2510Fx/CC2511Fx Specific SFR Overview 10.2.3.4 Radio Registers The radio ...

  • Page 48

    XDATA Register Description Address 0xDF16 BSCFG Bit Synchronization configuration 0xDF17 AGCCTRL2 AGC control 0xDF18 AGCCTRL1 AGC control 0xDF19 AGCCTRL0 AGC control 0xDF1A FREND1 Front end RX configuration 0xDF1B FREND0 Front end TX configuration 0xDF1C FSCAL3 Frequency synthesizer calibration 0xDF1D FSCAL2 ...

  • Page 49

    XDATA Register Address 0xDF40 I2SCFG0 0xDF41 I2SCFG1 0xDF42 I2SDATL 0xDF43 I2SDATH 0xDF44 I2SWCNT 0xDF45 I2SSTAT 0xDF46 I2SCLKF0 0xDF47 I2SCLKF1 0xDF48 I2SCLKF2 8 Registers without retention are in their reset state after PM2 or PM3. This is only applicable for registers ...

  • Page 50

    XDATA Register Address 0xDE10 USBMAXI USBCS0 0xDE11 USBCSIL 0xDE12 USBCSIH 0xDE13 USBMAXO 0xDE14 USBCSOL 0xDE15 USBCSOH USBCNT0 0xDE16 USBCNTL 0xDE17 USBCNTH Table 35: Overview of Indexed Endpoint Registers Table 36: Overview of Endpoint FIFO Registers 10.2.4 XDATA Memory Access CC2510Fx/CC2511Fx ...

  • Page 51

    MEMCTR (0xC7) - Memory Arbiter Control Bit Field Name Reset R/W 7:2 0 R/W 1 CACHDIS 0 R/W 0 PREFDIS 1 R/W 10.3 CPU Registers This section describes the internal registers found in the CPU. 10.3.1 Data Pointers CC2510Fx/CC2511Fx The ...

  • Page 52

    DPS (0x92) - Data Pointer Select Bit Field Name Reset R/W 7:1 0 R/W 0 DPS 0 R/W 10.3.2 Registers CC2510Fx/CC2511Fx The provides four register banks of eight registers each. These register banks are in the DATA ...

  • Page 53

    ACC (0xE0) - Accumulator Bit Field Name Reset R/W 7:0 ACC[7:0] 0x00 R/W 10.3.5 B Register The B register is used as the second 8-bit argument during execution of multiply and divide instructions. When not used for these B (0xF0) ...

  • Page 54

    Mnemonic Description Arithmetic Operations ADD A,Rn Add register to accumulator ADD A,direct Add direct byte to accumulator ADD A,@Ri Add indirect RAM to accumulator ADD A,#data Add immediate data to accumulator ADDC A,Rn Add register to accumulator with carry flag ...

  • Page 55

    Mnemonic Description XRL direct,#data Exclusive OR immediate data to direct byte CLR A Clear accumulator CPL A Complement accumulator RL A Rotate accumulator left RLC A Rotate accumulator left through carry RR A Rotate accumulator right RRC A Rotate accumulator ...

  • Page 56

    Mnemonic Description Program Branching ACALL addr11 Absolute subroutine call LCALL addr16 Long subroutine call RET Return from subroutine RETI Return from interrupt AJMP addr11 Absolute jump LJMP addr16 Long jump SJMP rel Short jump (relative address) JMP @A+DPTR Jump indirect ...

  • Page 57

    Clear to 0, “1” = Set to 1, “x” = Set to 1/Clear to 0, “-“ = Not affected Table 38: Instructions that Affect Flag Settings 10.5 Interrupts The CPU has 18 interrupt sources. Each source has its ...

  • Page 58

    Enable global interrupt by setting the IEN0.EA=1 5. Begin the interrupt service routine at the corresponding vector address of that interrupt. See Table addresses Interrupt Description Number done / RX ready 1 ADC end of conversion ...

  • Page 59

    Interrupt Description Number complete CC2511Fx 6 USB Interrupt pending ( CC2511Fx 13 USB resume interrupt ( P0_6 and P0_7 does not exist on CC2510Fx . USB resume interrupt configured like P0_7 interrupt on CC2510Fx 2 ...

  • Page 60

    IEN1 (0xB8) - Interrupt Enable 1 Register Bit Field Name Reset R R P0IE 0 R/W 4 T4IE 0 R/W 3 T3IE 0 R/W 2 T2IE 0 R/W 1 T1IE 0 R/W 0 DMAIE ...

  • Page 61

    IEN2 (0x9A) - Interrupt Enable 2 Register Bit Field Name Reset R/W 7:6 0 R/W 5 WDTIE 0 R/W 4 P1IE 0 R/W 3 UTX1IE / 0 R/W I2STXIE 2 UTX0IE 0 R/W 1 P2IE / 0 R/W USBIE 0 ...

  • Page 62

    When any module flag is cleared the chip will check if there are any module interrupt flags left that are both enabled and asserted the CPU interrupt flag will be asserted and a new interrupt triggered. ...

  • Page 63

    S0CON (0x98) - CPU Interrupt Flag 2 Bit Field Name Reset R/W 7:2 0 R/W 1 ENCIF_1 0 R/W 0 ENCIF_0 0 R/W S1CON (0x9B) - CPU Interrupt Flag 3 Bit Field Name Reset R/W 7:6 0 R/W 1 RFIF_1 ...

  • Page 64

    IRCON (0xC0) - CPU Interrupt Flag 4 Bit Field Name Reset STIF P0IF T4IF T3IF ...

  • Page 65

    IRCON2 (0xE8) - CPU Interrupt Flag 5 Bit Field Name Reset R/W 7:5 0 R/W 4 WDTIF 0 R/W 3 P1IF 0 R/W 2 UTX1IF / 0 R/W I2STXIF 1 UTX0IF 0 R/W 0 P2IF / 0 R/W USBIF 10.5.3 ...

  • Page 66

    IP0 (0xA9) - Interrupt Priority 0 Bit Field Name Reset R/W 7:6 0 R/W 5 IP0_IPG5 0 R/W 4 IP0_IPG4 0 R R/W IP0_IPG3 2 IP0_IPG2 0 R/W 1 IP0_IPG1 0 R/W 0 IP0_IPG0 0 R/W Group IPG0 ...

  • Page 67

    Interrupt Number Interrupt Name 0 RFTXRX DMA 1 ADC URX0 URX1 / I2SRX ENC P0INT / (USB Resume) 6 P2INT / USB 7 ...

  • Page 68

    Debug Interface CC2510Fx/CC2511Fx The includes an on-chip debug module which communicates over a two-wire interface. The debug interface allows programming of the on-chip flash. It also provides access to memory and registers contents, and debug features breakpoints, single-stepping, modification. ...

  • Page 69

    Note that after the Debug Lock bit has changed due to a Flash Information Page write or a flash mass erase, a HALT, RESUME, DEBUG_INSTR, STEP_INSTR, STEP_REPLACE command must be executed so that the Debug Lock value returned by READ_STATUS ...

  • Page 70

    Hardware Breakpoints The debug command SET_HW_BRKPNT is used to set a hardware breakpoint. The CC2510Fx/CC2511Fx supports hardware breakpoints. When a hardware breakpoint is enabled it will compare the CPU address bus with the breakpoint. When a match occurs, the ...

  • Page 71

    Bit Field Name Description 7:4 Not used. Must be set to 0000 3 TIMERS_OFF Disable timer operation (Timer 1/2/3/4). This overrides the TIMER_SUSPEND bit and its function DMA_PAUSE DMA pause TIMER_SUSPEND Suspend timers (Timer ...

  • Page 72

    Bit Field Name Description 7 CHIP_ERASE_DONE Flash chip erase done 0 Chip erase in progress 1 Chip erase done 6 PCON_IDLE PCON idle 0 CPU is running 1 CPU is idle (clock gated) 5 CPU_HALTED CPU halted 0 CPU running ...

  • Page 73

    Peripherals In the following sub-sections, CC2510Fx/CC2511Fx peripheral is described in detail. 12.1 Power Management and Clocks This section describes the Power Management Controller. The Power Management Controller controls the use of active mode, power modes, and clock control. 12.1.1 ...

  • Page 74

    Active Mode and Power Modes The different operating modes are described in detail in the five following sections. 12.1.2.1 Active Mode This is the full functional mode of operation where the CPU, peripherals, transceiver are active. The voltage regulator ...

  • Page 75

    SLEEP.MODE≠00 asserting PCON.IDLE should be as short as possible. The SLEEP.MODE will be cleared when power mode is entered, thus interrupts are enabled during power modes. All interrupts not to be used to wake ...

  • Page 76

    SLEEP (0xBE) - Sleep Mode Control Bit Field Name Reset R/W 7 USB_EN 0 R/W 6 XOSC_STB HFRC_STB 0 R 4:3 RST[1: OSC_PD 1 R/W H0 1:0 MODE[1:0] 00 R/W 12.1.5 Oscillators and Clocks ...

  • Page 77

    High Speed Oscillators Two high speed oscillators are present in the device: • High speed crystal oscillator ( CC2510Fx MHz for and 48 MHz for CC2511Fx ) • High speed RC oscillator (12 - 13.5 MHz CC2510Fx ...

  • Page 78

    Maximum Data Rate [kBaud] CLKCON.CLKSPD MSK GFSK 000 500 250 001 500 250 010 500 250 011 500 250 100 400 250 101 200 200 110 100 100 111 50 50 Table 49: System Clock Speed vs. Data Rate 12.1.5.3 ...

  • Page 79

    CLKCON (0xC6) - Clock Control Bit Field Name Reset R/W 7 OSC32K 1 R/W 6 OSC 1 R/W 5:3 TICKSPD[2:0] 001 R/W 2:0 CLKSPD[2:0] 001 R/W Description 32 kHz clock oscillator select. The HS RCOSC must be clock source for ...

  • Page 80

    Timer Tick Generation The power management controller generates a tick or enable signal for the peripheral timers, thus acting as a prescaler for the timers. This is a global clock division for Timer 1, Timer 2, Timer 3, and ...

  • Page 81

    The cause of the last reset can read from the register bits SLEEP.RST. It should be noted VOLT BOD RESET ASSERT POR RESET DEASSERT RISING VDD POR RESET ASSERT FALLING VDD 0 POR OUTPUT X BOD RESET POR RESET Figure ...

  • Page 82

    The DMA transfer method is the preferred way to write to the flash memory. A write operation is initiated by writing FCTL.WRITE. The address to start writing at is given by FADDRH:FADDRL. During each single write operation ...

  • Page 83

    When performing DMA flash write while executing code from within flash memory, the instruction that triggers the first DMA trigger event FLASH (TRIG[4:0]=10010) must be aligned on a 2-byte boundary. Figure 22 shows an example of code that correctly aligns ...

  • Page 84

    The steps required to start a CPU flash write operation are shown in Figure 23. Note that YES FCTL.SWBSY=1? Figure 23: CPU Flash Write Executed from RAM FCTL.SWBSY FCTL.BUSY Write two bytes to FWDATA (D0 and D1) 40 µs Set ...

  • Page 85

    Flash Controller has completed the operation. The flash erase operation requires that the instruction that starts the erase i.e. writing to ; Erase page 1 in ...

  • Page 86

    FCTL (0xAE) - Flash Control Bit Field Name Reset 7 BUSY 0 6 SWBSY CONTRD R/W 3 WRITE 0 0 ERASE 0 FWDATA (0xAF) - Flash Write Data Bit Field Name Reset 7:0 FWDATA[7:0] ...

  • Page 87

    I/O Ports Note: P0_6 and P0_7 do not exist on CC2511Fx The has 19 digital input/output pins available and the ADC inputs A6 and A7 can not be used. Apart from this, all information in this section applies to ...

  • Page 88

    Low I/O Supply Voltage In applications where the digital I/O power supply voltage VDD on pin DVDD is below 2.6 V, the register bit IOCFG1.GDO_DS should be set to 1. 12.4.4 General Purpose I/O Interrupts General purpose I/O pins ...

  • Page 89

    Periphery / P0 Function ADC USART0 Alt SPI Alt. 2 USART0 Alt UART Alt. 2 USART1 Alt ...

  • Page 90

    the user’s responsibility to make sure that there is a conclusive order of precedence based on the PERCFG and P2SEL settings. 12.4.6.2 USART1 The SFR bit PERCFG.U1CFG selects whether to use alternative 1 or alternative 2 ...

  • Page 91

    Timer 4 selects whether PERCFG.T4CFG alternative 1 or alternative 2 locations. In Table 50, the Timer 4 signals are shown as follows: • Channel 0 compare pin: 0 • Channel 1 compare pin: 1 P2SEL.PRI3P1, P2SEL.PRI2P1, P2SEL.PRI1P1, and P2SEL.PRI0P1 ...

  • Page 92

    PERCFG Peripheral Control • ADCCFG ADC Input Configuration • P0SEL Port 0 Function Select • P1SEL Port 1 Function Select • P2SEL Port 2 Function Select • P0DIR Port 0 Direction • P1DIR Port 1 Direction • P2DIR Port ...

  • Page 93

    ADCCFG (0xF2) - ADC Input Configuration Bit Field Name Reset R/W 7:0 ADCCFG[7:0] 0x00 R/W P0SEL (0xF3) - Port 0 Function Select Bit Field Name Reset R/W 7:0 SELP0_[7:0] 0x00 R/W P1SEL (0xF4) - Port 1 Function Select Bit Field ...

  • Page 94

    P2SEL (0xF5) - Port 2 Function Select Bit Field Name Reset R PRI3P1 0 R/W 5 PRI2P1 0 R/W 4 PRI1P1 0 R/W 3 PRI0P1 0 R/W 2 SELP2_4 0 R/W 1 SELP2_3 0 R/W 0 ...

  • Page 95

    P0DIR (0xFD) - Port 0 Direction Bit Field Name Reset R/W 7:0 DIRP0_[7:0] 0x00 R/W P1DIR (0xFE) - Port 1 Direction Bit Field Name Reset R/W 7:0 DIRP1_[7:0] 0x00 R/W P2DIR (0xFF) - Port 2 Direction Bit Field Name Reset ...

  • Page 96

    P2INP (0xF7) - Port 2 Input Mode Bit Field Name Reset 7 PDUP2 0 6 PDUP1 0 5 PDUP0 0 4:0 MDP2_[4:0] 00000 P0IFG (0x89) - Port 0 Interrupt Status Flag CC2510Fx Bit Field Name Reset 7:0 P0IF[7:0] 0x00 CC2511Fx ...

  • Page 97

    PICTL (0x8C) - Port Interrupt Control Bit Field Name Reset R R/W 5 P2IEN 0 R/W 4 P0IENH 0 R/W 3 P0IENL 0 R/W 2 P2ICON 0 R/W 1 P1ICON 0 R/W 0 P0ICON 0 ...

  • Page 98

    DMA Controller CC2510Fx/CC2511Fx The includes memory access (DMA) controller, which can be used to relieve the 8051 CPU core of handling data movement operations. Because CC2510Fx/CC2511Fx of this, the can achieve high overall performance with efficiency. The DMA controller ...

  • Page 99

    Initialization Write DMA channel configuration DMA Channel Idle No DMAARM.DMAARMn=1? Yes DMA Channel Armed Load DMA Channel configuration Trigger or DMAREQ.DMAREQn=1? Yes Transfer one byte or word when channel is granted access Modify source/destination address Reached transfer count? No Yes ...

  • Page 100

    The behavior of each of the five DMA channels is configured with the following parameters: 12.5.2.1 Source Address (SRCADDR) The address of the location in XDATA memory space where the DMA channel shall start to read data. 12.5.2.2 Destination Address ...

  • Page 101

    Byte/Word n+3 Byte/Word n+2 Byte/Word n+1 Byte/Word n Byte/Word n-1 Byte/Word n Byte/Word 3 Byte/Word 2 Byte/Word 1 Length = n VLEN = 001 If n ≥ LEN, LEN bytes/words are being transferred. The dotted line ...

  • Page 102

    The possibilities increment/decrement are: • Increment by zero. The address pointer shall remain fixed after each byte/word transfer. • Increment by one. The address pointer shall increment one count after each byte/word transfer. • Increment by two. The address ...

  • Page 103

    MOV DMAARM, #0x03 MOV DMAARM, #0x81 12.5.5 DMA Interrupts Each DMA channel can be configured to generate an interrupt to the CPU when the transfer count is reached. accomplished by setting the IRQMASK bit in the channel configuration to 1. ...

  • Page 104

    DMA Trigger DMA Trigger Functional Number Name Unit 18 FLASH Flash Controller 19 RADIO Radio 20 ADC_CHALL ADC 21 ADC_CH0 ADC 22 ADC_CH1 ADC 23 ADC_CH2 ADC 24 ADC_CH3 ADC 25 ADC_CH4 ADC 26 ADC_CH5 ADC ADC_CH6 ADC 27 2 ...

  • Page 105

    Byte Bit Field Name Offset 0 7:0 SRCADDR[15:8] 1 7:0 SRCADDR[7:0] 2 7:0 DESTADDR[15:8] 3 7:0 DESTADDR[7:0] 4 7:5 VLEN[2:0] 4 4:0 LEN[12:8] 5 7:0 LEN[7: WORDSIZE 6 6:5 TMODE[1:0] 6 4:0 TRIG[4:0] 7 7:6 SRCINC[1:0] 7 5:4 ...

  • Page 106

    Byte Bit Field Name Offset 7 3 IRQMASK 1:0 PRIORITY[1:0] Table 52: DMA Configuration Data Structure 12.5.8 DMA Registers This section describes the SFRs associated with the DMA Controller. DMAARM (0xD6) - DMA Channel Arm Bit ...

  • Page 107

    DMAREQ (0xD7) - DMA Channel Start Request and Status Bit Field Name Reset R/W 7 DMAREQ4 0 R/ DMAREQ3 0 R/ DMAREQ2 0 R/ DMAREQ1 0 R/ DMAREQ0 0 ...

  • Page 108

    DMAIRQ (0xD1) - DMA Interrupt Flag Bit Field Name Reset R/W 7 DMAIF4 0 R/W0 3 DMAIF3 0 R/W0 2 DMAIF2 0 R/W0 1 DMAIF1 0 R/W0 0 DMAIF0 0 R/W0 ENDIAN (0x95) - USB Endianess Control ...

  • Page 109

    Timer, Timer 1 Timer independent 16-bit timer which supports typical timer/counter functions such as input capture, output compare, and PWM functions. The timer has three independent capture/compare channels and uses one I/O pin per channel. ...

  • Page 110

    Modulo Mode In modulo mode the counter starts from 0x0000 and increments at each active clock edge. When the counter reaches the terminal count value T1CC0 (overflow), held in the registers T1CC0H:T1CC0L, the counter is loaded with 0x0000 on ...

  • Page 111

    Input Capture Mode When a channel is configured as an input capture channel, the I/O pin associated with that channel, is configured as an input. After the timer has been started, a rising edge, falling edge or any edge ...

  • Page 112

    The polarity of the PWM signal is determined by whether output compare mode used. PWM outputs Centre-aligned: generated when the timer up/down mode is selected. The channel output compare mode 3 Figure 32: Output Compare Modes, ...

  • Page 113

    Figure 33: Output Compare Modes, Timer Modulo Mode SWRS055F Page 113 of 241 ...

  • Page 114

    Figure 34: Output Modes, Timer Up/Down Mode 12.6.6 Timer 1 Interrupts There is one interrupt vector assigned to the timer. This is T1 (Interrupt #9, see 39). The following timer events may generate an interrupt request: • Counter reaches terminal ...

  • Page 115

    IEN1.T1EN. The interrupt mask bits are T1CCTL0.IM, T1CCTL1.IM, T1CCTL2.IM, and TIMIF.OVFIM. Note that enabling an interrupt mask bit will generate a new interrupt request if the corresponding interrupt flag is set. When the timer is used in ...

  • Page 116

    Table 53: Channel 0 Period Setting for some Sampling Rates (CLKCON.TICKSPD=000) Since the DSM starts immediately after DSM mode has been enabled T1CCTL1.CMP=111, all configuration should have been performed prior to enabling DSM mode. Also, the Timer 1 counter should ...

  • Page 117

    T1CNTH (0xE3) - Timer 1 Counter High Bit Field Name Reset R/W 7:0 CNT[15:8] 0x00 R T1CNTL (0xE2) - Timer 1 Counter Low Bit Field Name Reset R/W 7:0 CNT[7:0] 0x00 R/W T1CTL (0xE4) - Timer 1 Control and Status ...

  • Page 118

    T1CCTL0 (0xE5) - Timer 1 Channel 0 Capture/Compare Control Bit Field Name Reset R/W 7 CPSEL 0 R R/W 5:3 CMP[2:0] 000 R/W 2 MODE 0 R/W 1:0 CAP[1:0] 00 R/W T1CC0H (0xDB) - Timer 1 Channel ...

  • Page 119

    T1CCTL1 (0xE6) - Timer 1 Channel 1 Capture/Compare Control Bit Field Name Reset R/W 7 CPSEL 0 R R/W 5:3 CMP[2:0] 000 R/W 2 MODE 0 R/W 1:0 CAP[1:0] 00 R/W T1CC1H (0xDD) - Timer 1 Channel ...

  • Page 120

    T1CCTL2 (0xE7) - Timer 1 Channel 2 Capture/Compare Control Bit Field Name Reset R/W 7 CPSEL 0 R R/W 5:3 CMP[2:0] 000 R/W 2 MODE 0 R/W 1:0 CAP[1:0] 00 R/W T1CC2H (0xDF) - Timer 1 Channel ...

  • Page 121

    MAC Timer (Timer 2) The MAC timer is designed for slot timing operations used by the MAC layer protocol. The timer includes a highly tunable prescaler allowing the user to select a timer interval that equals, ...

  • Page 122

    T2CTL (0x9E) - Timer 2 Control Bit Field Name Reset R R TEX 0 R R/W 4 INT 0 R R/W 2 TIG 0 R/W 1:0 TIP[1:0] 00 R/W T2CT (0x9C) ...

  • Page 123

    Sleep Timer The Sleep Timer is used to control when the CC2510Fx/CC2511Fx exits from PM and hence the Sleep Timer can be used to implement a wake up functionality which CC2510Fx/CC2511Fx enables to periodically wake up to ...

  • Page 124

    If EVENT0 is changed to a value lower than the current counter value, WORCTRL.WOR_RESET has to be asserted first to reset the timer. The assertion of WORCTRL.WOR_RESET must be // Reset timer and enter PM{0 – 2} WORCTRL |= 0x04; ...

  • Page 125

    WORTIME1 (0xA6) - Sleep Timer High Byte Bit Name Reset 7:0 WORTIME[15:8] 0x00 WOREVT1 (0xA4) - Sleep Timer Event0 Timeout High Bit Field Name Reset 7:0 EVENT0[15:8] 0x87 WOREVT0 (0xA3) - Sleep Timer Event0 Timeout Low Bit Field Name Reset ...

  • Page 126

    Timers, Timer 3 and Timer 4 Timer 3 and Timer 4 are two 8-bit timers which supports typical timer/counter functions such as output compare and PWM functions. The timers have two independent channels each and use one I/O ...

  • Page 127

    Modulo Mode In modulo mode the counter starts from 0x00 and increments at each active clock edge. When the counter reaches the terminal count value TxCC0 (overflow), the counter is loaded with 0x00 on the next timer tick and ...

  • Page 128

    TxCC0 0x00 12.9.3 Channel Mode Control The channel mode is set with each channel’s control and status register TxCCTLn. Note: before an I/O pin can be used by the timer, the required I/O pin must be configured as a Timer ...

  • Page 129

    When the timer is used in Down Mode the interrupt flags are set as follows: • TIMIF.TxCH0IF TIMIF.TxCH1IF are set on compare event • TIMIF.TxOVFIF is set when counter reaches zero When the timer is used in Up/Down Mode the ...

  • Page 130

    T3CTL (0xCB) - Timer 3 Control Bit Field Name Reset R/W 7:5 DIV[2:0] 000 R/W 4 START 0 R/W 3 OVFIM 1 R/W0 2 CLR 0 R0/W1 1:0 MODE[1:0] 00 R/W Description Prescaler divider value. Generates the active clock edge ...

  • Page 131

    T3CCTL0 (0xCC) - Timer 3 Channel 0 Compare Control Bit Field Name Reset R R/W 5:3 CMP[2:0] 000 R/W 2 MODE 0 R/W 1:0 00 R/W T3CC0 (0xCD) - Timer 3 Channel 0 Compare ...

  • Page 132

    T3CCTL1 (0xCE) - Timer 3 Channel 1 Compare Control Bit Field Name Reset R R/W 5:3 CMP[2:0] 000 R/W 2 MODE 0 R/W 1:0 00 R/W T3CC1 (0xCF) - Timer 3 Channel 1 Compare ...

  • Page 133

    T4CTL (0xEB) - Timer 4 Control Bit Field Name Reset R/W 7:5 DIV[2:0] 000 R/W 4 START 0 R/W 3 OVFIM 1 R/W0 2 CLR 0 R0/W1 1:0 MODE[1:0] 00 R/W Description Prescaler divider value. Generates the active clock edge ...

  • Page 134

    T4CCTL0 (0xEC) - Timer 4 Channel 0 Compare Control Bit Field Name Reset R R/W 5:3 CMP[2:0] 000 R/W 2 MODE 0 R/W 1:0 00 R/W T4CC0 (0xED) - Timer 4 Channel 0 Compare ...

  • Page 135

    T4CCTL1 (0xEE) - Timer 4 Channel 1 Compare Control Bit Field Name Reset R R/W 5:3 CMP[2:0] 000 R/W 2 MODE 0 R/W 1:0 00 R/W T4CC1 (0xEF) - Timer 4 Channel 1 Compare ...

  • Page 136

    TIMIF (0xD8) - Timers 1/3/4 Interrupt Mask/Flag Bit Field Name Reset R OVFIM 1 R/W 5 T4CH1IF 0 R/W0 4 T4CH0IF 0 R/W0 3 T4OVFIF 0 R/W0 2 T3CH1IF 0 R/W0 1 T3CH0IF 0 R/W0 0 ...

  • Page 137

    ADC 12.10.1 ADC Introduction The ADC supports up to 12-bit analog-to- digital conversion. The ADC includes an analog multiplexer with up to eight individually configurable channels, reference generator, and conversion results written to memory through DMA. Several modes of ...

  • Page 138

    It is also possible to select a voltage corresponding to VDD ADC input. This input allows the implementation of e.g. a battery monitor in applications where this feature is required. 12.10.2.3 ADC Conversion Sequences The ADC will perform ...

  • Page 139

    Note: P0_6 and P0_7 do not exist on CC2511Fx , hence it is not possible to use external voltage reference for the ADC on CC2511Fx . the 12.10.2.6 ADC Conversion Results The digital conversion result is represented in two's complement ...

  • Page 140

    ADCL (0xBA) - ADC Data Low Bit Field Name Reset R/W 7:4 ADC[3:0] 0000 R 3:0 0000 R ADCH (0xBB) - ADC Data High Bit Field Name Reset R/W 7:0 ADC[11:4] 0x00 R ADCCON1 (0xB4) - ADC Control 1 Bit ...

  • Page 141

    ADCCON2 (0xB5) - ADC Control 2 Bit Field Name Reset R/W 7:6 SREF[1:0] 00 R/W 5:4 SDIV[1:0] 01 R/W 3:0 SCH[3:0] 00 R/W Description Selects reference voltage used for the sequence of conversions 00 Internal 1.25 V reference 01 External ...

  • Page 142

    ADCCON3 (0xB6) - ADC Control 3 Bit Field Name Reset R/W 7:6 EREF[1:0] 00 R/W 5:4 EDIV[1:0] 00 R/W 3:0 ECH[3:0] 0000 R/W Description Selects reference voltage used for the extra conversion 00 Internal 1.25V reference 01 External reference on ...

  • Page 143

    Random Number Generator 12.11.1 Introduction The random number generator has the following features. • Generate pseudo-random bytes which can be read by the CPU. • Calculate CRC16 of bytes that are written to RNDH. • Seeded by value written ...

  • Page 144

    RNDL (0xBC) - Random Number Generator Data Low Byte Bit Field Name Reset R/W [7:0] RNDL[7:0] 0xFF R/W RNDH (0xBD) - Random Number Generator Data High Byte Bit Field Name Reset R/W [7:0] RNDH[7:0] 0xFF R/W 12.12 AES Coprocessor CC2510Fx/CC2511Fx ...

  • Page 145

    Read/write to the control and status register is done by the CPU, while read/write the output/input registers is intended for use together with direct memory access (DMA). When using DMA, one channel is used for input data and one for ...

  • Page 146

    ENCCS (0xB3) - Encryption Control and Status Bit Field Name Reset R 6:4 MODE[2:0] 000 R/W 3 RDY 1 R 2:1 CMD[1: R/W1 H0 ENCDI (0xB1) - Encryption Input Data Bit Field ...

  • Page 147

    Watchdog Timer The watchdog timer (WDT) is intended as a recovery method in situations where the software hangs. The WDT shall reset the system when software fails to clear the WDT within a selected time interval. The watchdog can ...

  • Page 148

    Power Mode Comments PM1 The WDT runs but does not reset the chip upon timeout. If active mode is entered just as the timer expires, the chip will be reset immediately, hence the ...

  • Page 149

    USART USART0 and USART1 communications interfaces that operated separately in either asynchronous UART mode or in synchronous SPI mode. The two USARTs are identical in functionality but are assigned to separate I/O pins. Refer to Section 12.4 on Page ...

  • Page 150

    UxCSR is read. The receiver will check both stop bits when UxUCR.SPB=1. Note that the USARTx RX complete CPU interrupt flag, TCON.URXxIF, and the UxCSR.RX_BYTE bit will be asserted when the first stop bit is checked OK. If the second ...

  • Page 151

    Slave Select pin (SSN) When the USART is operating in SPI slave mode, a 4-wire interface is used with the Slave Select (SSN) pin as an input to the SPI (edge controlled). The SPI slave becomes active after a ...

  • Page 152

    SPI rate (UxGCR.BAUD_E[4:0]=19 UxBAUD.BAUD_M[7:0]=0). baud rates than this will give erroneous results. For SPI slave mode the maximum baud rate is always F/8. Baud Rate [bps] 2400 4800 9600 14400 19200 28800 38400 57600 76800 115200 230400 Table 55: ...

  • Page 153

    The interrupt enables and summarized below. Interrupt enable bits: • USART0 RX : IEN0.URX0IE • USART1 RX : IEN0.URX1IE • USART0 TX : IEN2.UTX0IE • USART1 TX : IEN2.UTX1IE Interrupt flags: • USART0 RX : TCON.URX0IF • USART1 RX : ...

  • Page 154

    U0CSR (0x86) - USART 0 Control and Status Bit Field Name Reset R/W 7 MODE 0 R R/W 5 SLAVE 0 R R/W0 3 ERR 0 R/W0 2 RX_BYTE 0 R/W0 1 TX_BYTE 0 ...

  • Page 155

    U0UCR (0xC4) - USART 0 UART Control Bit Field Name Reset R/W 7 FLUSH 0 R0 FLOW 0 R R/W 4 BIT9 0 R/W 3 PARITY 0 R/W 2 SPB 0 R/W 1 STOP 1 ...

  • Page 156

    U0GCR (0xC5) - USART 0 Generic Control Bit Field Name Reset R/W 7 CPOL 0 R/W 6 CPHA 0 R/W 5 ORDER 0 R/W 4:0 BAUD_E[4:0] 00000 R/W U0DBUF (0xC1) - USART 0 Receive/Transmit Data Buffer Bit Field Name Reset ...

  • Page 157

    U1CSR (0xF8) - USART 1 Control and Status Bit Field Name Reset R/W 7 MODE 0 R R/W 5 SLAVE ERR 0 R RX_BYTE 0 R/W 0 ...

  • Page 158

    U1UCR (0xFB) - USART 1 UART Control Bit Field Name Reset R/W 7 FLUSH 0 R0 FLOW 0 R R/W 4 BIT9 0 R/W 3 PARITY 0 R/W 2 SPB 0 R/W 1 STOP 1 ...

  • Page 159

    U1DBUF (0xF9) - USART 1 Receive/Transmit Data Buffer Bit Field Name Reset R/W 7:0 DATA[7:0] 0x00 R/W U1BAUD (0xFA) - USART 1 Baud Rate Control Bit Field Name Reset R/W 7:0 BAUD_M[7:0] 0x00 R/W 2 12. CC2510Fx/CC2511Fx The ...

  • Page 160

    I2SSTAT register. The interrupt enables and flags are summarized below. Interrupt enable bits: 2 • RX: I2SCFG0.RXIEN 2 • TX: I2SCFG0.TXIEN Interrupt flags: 2 • RX: I2SSTAT.RXIRQ 2 • ...

  • Page 161

    I2SDATH I2SDATH register indicates the completion of the read operation. 2 When the configured to receive stereo, i.e. I2SCFG0.RXMONO I2SSTAT.RXLR flag can be used to determine whether the sample currently in the ...

  • Page 162

    F (kHz) Word Size ( 44 Table 58: Example I 12.15.8.2 Word Size The word size must be set before master mode is enabled. The word size is the number of bits ...

  • Page 163

    I2SCFG0.ULAWE bit When the I S interface is enabled, i.e. the I2SCFG0.ENAB bit is 1, and µ-Law expansion is enabled, every byte of µ-Law compressed data written to the I2SDATH register is expanded ...

  • Page 164

    I2SCFG0 - I S Configuration Register 0 Bit Field Name Reset R/W 7 TXIEN 0 R/W 6 RXIEN 0 R/W 5 ULAWE 0 R/W 4 ULAWC 0 R/W 3 TXMONO 0 R/W 2 RXMONO 0 R/W 1 MASTER ...

  • Page 165

    I2SCFG1 - I S Configuration Register 1 Bit Field Name Reset R/W 7:3 WORDS[4:0] 01111 R/W 2:1 TRIGNUM[1:0] 00 R/W 0 IOLOC 0 R/W 2 0xDF42: I2SDATL - I S Data Low Byte Bit Field Name Reset R/W ...

  • Page 166

    I2SSTAT - I S Status Register Bit Field Name Reset R/W 7 TXUNF 0 R/W 6 RXOVF 0 R/W 5 TXLR RXLR TXIRQ 0 R/ RXIRQ 0 R/W1 H0 1:0 ...

  • Page 167

    USB Controller Note: The USB controller is only available CC2511Fx on the . CC2511Fx contains The a Full-Speed USB 2.0 compatible USB controller communication with other equipment with USB host functionality. Note: This section will focus ...

  • Page 168

    See 12.1.5.1 for details on how to set up the crystal oscillator. 12.16.2 USB Enable The USB Controller must be enabled before it is used. This is performed by setting the bit to SLEEP.USB_EN Interrupt Flag Description USBCIF Contains ...

  • Page 169

    Endpoint 0 is controlled through the USBCS0 register by setting the USBINDEX register to 0. The USBCNT0 register contains the number of bytes received. 12.16.5 Endpoint 0 Interrupts The following events may generate an EP0 interrupt request: • A data ...

  • Page 170

    Unload the Setup Packet from the EP0 FIFO 2. Examine the contents and perform the appropriate operations 3. Set the USBCS0.CLR_OUTPKT_RDY bit to 1. This denotes the end of the Setup stage. If the control transfer has no Data ...

  • Page 171

    OUT endpoints. Each IN and OUT endpoint can be configured as either Isochronous (USBCSIH.ISO=1 or USBCSOH.ISO=1) (USBCSIH.ISO=0 endpoints. USBCSOH.ISO=0) Interrupt endpoints are handled identically by the USB controller but will have different properties from a firmware perspective. ...

  • Page 172

    However, the data packet may be sent/received at any time during the USB frame period and there is a chance that two data packets may be sent/received at a few micro seconds interval. For endpoints, an incoming packet will ...

  • Page 173

    The following events may generate an OUT EPx interrupt request: • A data packet has been received (USBCSOL.OUTPKT_RDY=1) • A STALL has (USBCSIL.SENT_STALL=1). Bulk/Interrupt endpoints can be stalled Any of these events to USBOIF.OUTEPxIF regardless of the status of the ...

  • Page 174

    An isochronous data packet in the OUT FIFO may have bit errors. The hardware will detect this condition and set USBCSOL.DATA_ERROR. Firmware should therefore always check this bit when unloading a data packet. The AutoClear feature will typically not be ...

  • Page 175

    USB Reset When reset signaling is detected on the bus, the USBCIF.RSTIF flag will be asserted. If USBCIE.RSTIE is enabled, IRCON2.USBIF will also be asserted and an interrupt request is generated if IEN2.USBIE=1. The firmware should take appropriate action ...

  • Page 176

    USBADDR - Function Address Bit Field Name Reset 7 UPDATE 0 6:0 USBADDR[6:0] 0000000 0xDE01: USBPOW - Power/Control Register Bit Field Name Reset 7 ISO_WAIT_SOF 0 6 RST 0 2 RESUME 0 1 SUSPEND 0 0 SUSPEND_EN ...

  • Page 177

    USBCIF - Common USB Interrupt Flags Bit Field Name Reset R/W 7 SOFIF RSTIF RESUMEIF SUSPENDIF 0xDE07: USBIIE - IN Endpoints ...

  • Page 178

    USBOIE - Out Endpoints Interrupt Enable Mask Bit Field Name Reset R/W 7:6 00 R/W 5 OUTEP5IE 1 R/W 4 OUTEP4IE 1 R/W 3 OUTEP3IE 1 R/W 2 OUTEP2IE 1 R/W 1 OUTEP1IE 1 R 0xDE0B: ...

  • Page 179

    USBFRMH - Current Frame Number (High byte) Bit Field Name Reset 7:3 - 2:0 FRAME[10:8] 000 0xDE0E: USBINDEX - Current Endpoint Index Register Bit Field Name Reset 7:4 - 3:0 USBINDEX[3:0] 0000 0xDE10: USBMAXI - Max. Packet Size for ...

  • Page 180

    USBCSIL - IN EP Control and Status Low Bit Field Name Reset CLR_DATA_TOG 0 5 SENT_STALL 0 4 SEND_STALL 0 3 FLUSH_PACKET 0 2 UNDERRUN 0 1 PKT_PRESENT 0 0 INPKT_RDY 0 0xDE12: USBCSIH ...

  • Page 181

    USBCSOL - OUT EP Control and Status Low Bit Field Name Reset 7 CLR_DATA_TOG 0 6 SENT_STALL 0 5 SEND_STALL 0 4 FLUSH_PACKET 0 3 DATA_ERROR 0 2 OVERRUN 0 1 FIFO_FULL 0 0 OUTPKT_RDY 0 0xDE15: ...

  • Page 182

    USBCNTH - Number of Bytes in EP{1 – 5} OUT FIFO High Bit Field Name Reset R/W 7 2:0 USBCNT[10:8] 000 R 0xDE20: USBF0 - Endpoint 0 FIFO Bit Field Name Reset R/W 7:0 USBF0[7:0] 0x00 R/W ...

  • Page 183

    Radio LNA RF_P RF_N PA Figure 47: CC2510Fx/CC2511Fx Radio Module A simplified block diagram of the radio module CC2510Fx/CC2511Fx in the is shown in Figure 47. CC2510Fx/CC2511Fx features a low-IF receiver. The received RF signal is amplified by the ...

  • Page 184

    Default state when the radio is not receiving or transmitting.. Used for calibrating frequency synthesizer upfront (entering Manual freq. receive or transmit mode can synth. calibration then be done quicker). Transitional state. Frequency synthesizer is on, ready to start transmitting. ...

  • Page 185

    RFST Command Description Value Strobe Name 0x00 SFSTXON Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=01 (with CCA wait state where only the synthesizer is running (for quick turnaround). 0x01 SCAL Calibrate ...

  • Page 186

    Packet received/transmitted. Also used to detect overflow/underflow conditions • CS • PQT reached • CCA • SFD Each of these events has a corresponding interrupt flag in the RFIF register which is asserted when the event occurs. If the ...

  • Page 187

    RFIM (0x91 Interrupt Mask Bit Field aName Reset R/W 7 IM_TXUNF 0 R/W 6 IM_RXOVF 0 R/W 5 IM_TIMEOUT 0 R/W 4 IM_DONE 0 R/W 3 IM_CS 0 R/W 2 IM_PQT 0 R/W 1 IM_CCA 0 R/W 0 ...

  • Page 188

    A simple example of transmitting data is shown ; Transmit the following data: 0x02, 0x12, 0x34 ; (Assume that the radio has already been configured, the high speed ; crystal oscillator is selected as system clock, and CLKCON.CLKSPD=000) RFST,#03H MOV ...

  • Page 189

    MDMCFG4. MDMCFG4.CHANBW_E CHANBW_M 00 01 812 406 00 650 325 01 541 270 10 464 232 11 Table 62: Channel Filter Bandwidths [kHz] (assuming MHz) ref 13.7 Demodulator, Symbol Synchronizer, and Data Decision CC2510Fx/CC2511Fx contains an advanced ...

  • Page 190

    Packet Handling Hardware Support CC2510Fx/CC2511Fx The has built-in hardware support for packet oriented radio protocols. In transmit mode, the packet handler can be configured to add the following elements to the packet: • A programmable number of preamble bytes ...

  • Page 191

    XOR-ed with a 9-bit pseudo-random (PN9) sequence before being transmitted as shown in Figure 50. At the receiver end, the data are XOR-ed with the same sequence. This way, the whitening is reversed, 13.8.2 Packet Format The format of the ...

  • Page 192

    The preamble pattern is an alternating sequence of ones and zeros (101010101…). The minimum length of the preamble is programmable through the NUM_PREAMBLE field in the MDMCFG1 register. When enabling TX, the modulator will start transmitting the preamble. When the ...

  • Page 193

    If FEC/Interleaving is enabled, everything following the sync words will be scrambled by the interleaver and FEC encoded before being modulated. FEC is enabled MDMCFG1.FEC_EN=1. 13.8.5 Packet Handling in Receive Mode In receive mode, the demodulator and packet handler will ...

  • Page 194

    Minimum Shift Keying 21 When using MSK the complete transmission (preamble, sync word, and payload) will be MSK modulated. Phase shifts are performed with a constant transition time. The fraction of a symbol period used to change the phase ...

  • Page 195

    Note: It takes some time from the radio enters RX mode until a valid RSSI value is present in the RSSI register. Please see DN505 [12] for details on how the RSSI response time can be estimated. The RSSI value ...

  • Page 196

    Carrier Sense can be used as a sync word qualifier that requires the signal level to be higher than the threshold for a sync word search to be performed. The signal can also be observed on P1_5, P1_6, or P1_7 ...

  • Page 197

    Clear Channel Assessment (CCA) The Clear Channel Assessment CCA) is used to indicate if the current channel is free or busy. The current CCA state is viewable on P1_5, P1_6, or P1_7 IOCFGx.GDOx_CFG=1001. MCSM1.CCA_MODE selects the mode to use ...

  • Page 198

    CC2510Fx/CC2511Fx employs matrix interleaving, which is illustrated in Figure 53. The on-chip interleaving and de-interleaving buffers are matrices. In the transmitter, the data bits from the rate ½ convolutional coder are written into the rows of the ...

  • Page 199

    Figure 54: Complete Radio Control State Diagram SWRS055F Page 199 of 241 ...

  • Page 200

    Active Modes The radio has two active modes: receive and transmit. These modes are activated directly by writing the SRX and STX command strobes to the RFST register. The frequency synthesizer must be calibrated CC2510Fx/CC2511Fx regularly. has one manual ...