SI4421-A1-FT Silicon Laboratories Inc, SI4421-A1-FT Datasheet
SI4421-A1-FT
Specifications of SI4421-A1-FT
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SI4421-A1-FT Summary of contents
Page 1
... I/Q demodulator. All required RF functions are integrated. Only an external crystal and bypass filtering are needed for operation. The Si4421 features a completely integrated PLL for easy RF design, and its rapid settling time allows for fast frequency-hopping, bypassing multipath fading and interference to achieve robust wireless links. The PLL’ ...
Page 2
... DETAILED FEATURE-LEVEL DESCRIPTION The Si4421 FSK transceiver is designed to cover the unlicensed frequency bands at 433, 868 and 915 MHz. The device facilitates compliance with FCC and ETSI requirements. The receiver block employs the Zero-IF approach with I/Q demodulation, allowing the use of a minimal number of external components in a typical application ...
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... Higher data rate Inexpensive crystals Crystal Oscillator The Si4421 has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet. The transceiver can supply a clock signal for the microcontroller ...
Page 4
... AIO RF differential signal input/output 14 VDD S Positive supply voltage 15 ARSSI AO Analog RSSI output nINT DI Interrupt input (active low) 16 VDI DO Valid data indicator output Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O settings of the transceiver. Si4421 4 ...
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... Internal Pin Connections Pin Name Internal connection 1 SDI VDD 2 SCK PAD 1.5k 3 nSEL VSS 4 SDO 5 nIRQ FSK 6 DATA nFFS DLCK 7 CFIL FFIT VDD 8 CLK PAD 10 VSS XTL 9 REF Pin Name Internal connection 10 nRES 11 VSS 12 RF2 13 RF1 14 VDD 15 ARSSI nINT 16 VDI Si4421 5 ...
Page 6
... PIN6 Logic Diagram (FSK / DATA / nFFS) PIN10 Logic Diagram (nRES I/O) * Note: These pins can be left floating. Si4421 6 ...
Page 7
... P0 (optional CLK nRES (optional) Note: * Connections needed only in time critical applications C3 Property 220pF SMD size 47pF Dielectric 33pF Function (TX data register can be accessed) (RX data FIFO can be accessed) Si4421 C3 C2 10n C4 2.2n (opt.) PCB Antenna X1 10MHz 0603 0603 Tantalum Ceramic Ceramic ...
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... Note 2: The actual voltage on RF1 and RF2 pins can be lower than the current V Min Max Units -0.5 6 -0.5 V +0.5 dd -0.5 V +1.5 (Note 1) dd -25 25 1000 -55 125 260 Min Max Units 2.2 3.8 V -1.5 (Note -40 85 but cannot exceed but never should go below 1 Si4421 ...
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... MHz band 433 MHz band 868 MHz band 915 MHz band 433 MHz band 868 MHz band 915 MHz band All blocks disabled Crystal oscillator on (Note 1) Programmable in 0.1 V steps 2.25 0.7· 3 Si4421 Min Typ Max Units 0.3 1 µA 0.5 1.7 µA 1 ...
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... MHz o LNA: high gain When input signal level lower than -54 dBm and greater than -100 dBm Until the RSSI signal goes high after the input signal exceeds the preprogrammed limit C = 4.7 nF ARRSI Si4421 Min Typ Max Units MHz 439.75 MHz 879 ...
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... Synthesizer and crystal oscillator on during RX/TX change with 10 MHz step Conditions/Notes Programmable in 0.5 pF steps, tolerance ± 10% After V has reached 90% of final value dd (Note 8) Crystal oscillator must be enabled to ensure proper calibration at the start up. (Note pure capacitive load Si4421 Min Typ Max Units 0 dBm 5 7 dBm ...
Page 12
... Command, page 25) the reset timeout is 0.25ms typical. Note 9: The crystal oscillator start up time strongly depends on the capacitance seen by the oscillator. Low capacitance and low ESR crystal is recommended with low parasitic PCB layout design. Note 10: By design Z [Ohm] L [nH] antenna antenna 52 + j152 62 7.8 + j83 15 j77 13.6 Si4421 12 ...
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... Data setup time (SDI transition to SCK rising edge Data hold time (SCK rising edge to SDI transition Data delay time OD Timing Diagram t SS nSEL SCK SDI BIT 15 BIT 14 BIT 13 SDO FFIT FFOV BIT 8 BIT 7 BIT 1 CRL AT S OFFS(0) Si4421 Minimum value [ns SHI t SH BIT 0 FIFO OUT 13 ...
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... C22Ch CA80h CED4h B000h C4F7h 9800h CC77h B8AAh E196h C80Eh C000h 0000h Si4421 Related control bits el er, ebb, et, es, ex, eb, ew, dc f11 p16 al, ml f0, sp, ff, al a0, rl1 to rl0, st, fi, oe ob1 to ob0, ddit, dly, bw0 ...
Page 15
... Related blocks RF front end, baseband, synthesizer, crystal oscillator Baseband Power amplifier, synthesizer, crystal oscillator Synthesizer Crystal oscillator Low battery detector Wake-up timer Clock output buffer Si4421 POR 8008h x0 Crystal Load Capacitance [pF] 0 8.5 1 9.0 0 9.5 1 10.0 … 0 15.5 1 16.0 ...
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... VCO and RF synthesizer PLL start TX TX latch clear TX latch enable Crystal crystal oscillator oscillator Digital signal processing clock and data out Si4421 enable RF front end enable baseband circuits I/Q demod 16 ...
Page 17
... BR/BR < 1/(29 · Clock recovery in fast mode: bit BR is the bit rate difference between the transmitter and the receiver p16 Function of pin 16 0 Interrupt input 1 VDI output Si4421 POR A680h Band [MHz 433 1 43 868 2 43 915 3 30 PLL Frequency Step 2 ...
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... Medium 1 0 Slow 1 1 Always on MUX DQD d0 SEL0 d1 SEL1 FAST IN0 MEDIUM IN1 SLOW IN2 LOGIC HIGH IN3 CLR SET R/S FF CLR Note: * For details see the Power Management Command [kHz Reserved 400 340 270 200 134 Reserved Si4421 VDI Y 18 ...
Page 19
... Note: If analog RC filter is selected the internal clock recovery circuit and the FIFO cannot be used Gain relative to maximum [ RSSI setth -103 - - - - - Reserved Reserved Filter Type 0 Digital filter 1 Analog RC filter 2.4 4.8 9.6 19.2 8.2 nF 6.8 nF 3.3 nF 1.5 nF Si4421 POR C22Ch 38.4 57.6 115.2 256 680 pF 270 pF 150 pF 100 pF 19 ...
Page 20
... Note: The synchron pattern consists of one or two bytes depending on the sp bit. Byte1 is fixed 2Dh, Byte0 can be programmed by the Synchron Pattern Command (page 21). Bit 2 (al): Set the input of the FIFO fill start condition bit rate offset Byte1 Byte0 (POR) Synchron Pattern (Byte1+Byte0) 2Dh D4h D4h al FIFO fill start condition 0 Synchron pattern 1 Always fill Si4421 POR CA80h 2DD4h D4h 20 ...
Page 21
... Operation mode Auto mode off (Strobe is controlled by microcontroller) Runs only once after each power-up Keep the f only during receiving (VDI=high) offset Keep the f value independently from the state of the VDI signal offset Si4421 POR CED4h POR B000h . ref 3 ...
Page 22
... The main benefits of the automatic frequency control: cheap crystal can be used, the temperature or aging drift will not cause range loss and no production alignment needed res 433 MHz bands: 2.5 kHz to -16 f res 868 MHz band: 5 kHz res 915 MHz band: 7.5 kHz res Si4421 22 ...
Page 23
... Antenna Application Note: IA ISM-AN1 out mp=0 and FSK=0 mp=1 and FSK=1 0 Note: FSK represents the value of the actual data bit Si4421 POR 9800h df df fsk fsk f out f 0 mp=0 and FSK mp=1 and FSK=0 ...
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... Note: Alternately the transmit register can be directly accessed by nFFS (pin6 ob1 ob0 1 ob1 ob0 Selected µC CLK frequency MHz (recommended 3.3 MHz 0 X 2.5 MHz or less Phase noise at 1MHz offset [dBc/Hz] 86.2 -107 256 -102 BYTE1 TX BYTE2 Si4421 POR dly ddit 1 bw0 CC77h POR B8AAh TX BYTEn 24 ...
Page 25
... Choosing too short on-time can prevent the crystal oscillator from starting or the DQD signal will not go high even when the received signal has good quality. There is an application proposal on page 26. The Si4421 is configured to work in FIFO mode. The chip periodically wakes up and switches to receiving mode. If valid FSK data received, the chip sends an interrupt to the microcontroller and continues filling the RX FIFO ...
Page 26
... The 4-bit parameter (v3 to v0) represents the value V, which defines the threshold voltage 2. · 0.1 [V] lb Clock divider configuration: The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power Management Command (page 15 Clock Output Frequency [MHz Si4421 POR C000h of the detector ...
Page 27
... The AFC offset value (OFFS bits in the status word) is represented as a two’s complement number. The actual frequency offset can be calculated as the AFC offset value multiplied by the current PLL frequency step (see the Frequency Setting Command on page 17 Function Si4421 POR 0000h 27 ...
Page 28
... WKUP: both the nIRQ pin and status bit can be cleared by the read status command EXT: both the nIRQ pin and status bit follow the level of the nINT pin LBD: the nIRQ pin can be released by the reading the status, but the status bit will remain active while the VDD is below the threshold. Si4421 28 ...
Page 29
... Also, the Si4421 will not go to low current sleep mode if any interrupt remains active regardless to the state of the ex (enable crystal oscillator) bit in the Power Management Command (page 15). This way the microcontroller always can have clock signal to process the interrupt ...
Page 30
... It is possible to perform this sequence without sending a dummy byte (step i.) but after loading the last data byte to the transmit register the PA turn off should be delayed for at least 16 bits time. The clock source of the microcontroller (if the clock is not supplied by the Si4421) should be stable enough over temperature and voltage to ensure this minimum delay under all operating circumstances. ...
Page 31
... SCK nFFS FIFO read out SDO FIFO OUT FO+1 FO+2 FO+3 FO+4 FFIT /4, where f is the crystal oscillator frequency. When the duty-cycle of the ref ref Synchron word (Can be network ID) D4h (programmable) 2DD4h (D4 is programmable) Si4421 . ref Payload CRC ? 4 bit - 1 byte ? 2 byte 31 ...
Page 32
... CRYSTAL SELECTION GUIDELINES The crystal oscillator of the Si4421 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can variety of crystal types can be used ...
Page 33
... It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the receiver. By reading out the status byte from the receiver, the actual measured offset frequency will be reported. In order to get accurate values the AFC has to be disabled during the read by clearing the en bit in the AFC Control Command (page 21). Si4421 33 ...
Page 34
... During this period, the chip dd line if the supply filtering is not satisfactory or the internal resistance of the power supply level reaches the reset threshold voltage (250mV dd must drop below 250mV in order to trigger a power-on reset dd Si4421 voltage dd and the internal ramp dd dd reaches the reset ...
Page 35
... Issuing FE00h command will trigger software reset (sensitive reset mode must be enabled). See the Wake-up Timer Command (page 25). Reset threshold voltage (600mV) Reset ramp line (100mV/ms) Reset threshold voltage (600mV) ramp start.. Typical example when a switch-mode dd line. Follow the manufacturer’s recommendations dd Si4421 time Reset ramp line (100mV/ms) time 35 ...
Page 36
... The ETSI limit given in the figure is drawn by taking -106dBm at 9.6kbps typical sensitivity into account, and corresponds to receiver class 2 requirements (section 4.1.1) Phase Noise Performance in the 433, 868 and 915 MHz Bands: (Measured under typical conditions interferer offset from carrier [MHz] 433 MHz 868 MHz 915 MHz = 2 Si4421 434 MHz 868 MHz ETSI 2 ...
Page 37
... FSK FSK FSK -110 -105 -100 -105 -100 -95 9.6 kbps 19.2 kbps BW=67 kHz BW=67 kHz f f =45kHz =45 kHz =45 kHz FSK FSK Si4421 1.2k 2.4k 4.8k 9.6k 19.2k 38.4k 57.6k 115.2k -95 -90 1.2k 2.4k 4.8k 9.6k 19.2k 38.4k 57.6k 115.2k -90 ...
Page 38
... Receiver Sensitivity over Ambient Temperature (868 MHz, 2.4 kbps, -100 -103 -106 -109 -112 -115 -50 434 MHz - Celsius 868 MHz - Celsius Si4421 kHz, BW: 67 kHz): FSK 2.2V 2.7V 3.3V 3.8V 75 100 kHz, BW: 67 kHz): FSK 2.2V 2.7V 3.3V 3.8V 100 38 ...
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... Part number 434MHz 868 MHz 0603CS-18NX 0603CS-3N9X 0603CS-18NX 0603CS-3N9X 0603CS-47NX 0603CS-18NX 0603CS-R39X 0603CS-R10X GRM1885C1H1R2CZ01B GRM1885C1H2R7CZ01B GRM1885C1H1R8CZ01B GRM1885C1H470JZ01B GRM1885C1H470JZ01B Si4421 * C8 MATCHING_NETWORK GND * GND * C10 * GND * GND * * C9 C11 CN62 optional ANT GND * * See values in the table VDD ...
Page 40
... The dielectric type should be C0G and the resonant frequency should be similar if components from alternative vendor used. 4. The values are valid for 1.5mm thick FR4 PCB. If thinner board used the capacitor value should be increased (and vice versa) to minimize the level of the second harmonic components. PCB Layout Top View Bottom View Si4421 40 ...
Page 41
... NINT/VDI SCK 2 SCK ARSSI SEL 3 NSEL VDD SDO 4 SDO RF1 C1 IRQ 5 NIRQ RF2 2.2uF DATA 6 FSK/DATA/NFFS VSS DCLK 7 DCLK/CFIL NRES R5 DTO 8 CLK XTL/REF 10k C6 IA4421 100pF TP3 TP1 GND Si4421 GND 16 VDI 15 ARSSI RESET 9 * See values in the table JP1 CLKIN GND 41 ...
Page 42
... PCB Layout (Antenna designed for 868/915 MHz band) Top View Bottom View Si4421 42 ...
Page 43
... 6.40 BSC. 4,40 4,50 0,169 0,60 0,75 0,020 1.00 REF REF. 12 REF. Si4421 0.25 Detail “A” ” Nom. Max 0,035 0,041 0,009 0,010 0,197 0,201 0.252 BSC. 0,173 0,177 0,024 0,030 0.39 REF REF. ...
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... RELATED PRODUCTS AND DOCUMENTS Si4421 Universal ISM Band FSK Transceiver DESCRIPTION Si4421 16-pin TSSOP Demo Boards and Development Kits DESCRIPTION Development Kit ISM Repeater Demo Related Resources DESCRIPTION Antenna Selection Guide Antenna Development Guide Si4221 Universal ISM Band FSK Transmitter Si4320 Universal ISM Band FSK Receiver Note: Volume orders must include chip revision to be accepted ...
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... Si4421 45 ...