ATA5773-PXQW Atmel, ATA5773-PXQW Datasheet - Page 133

• Manufacturer Part Number: ATA5773-PXQW
• Description: XMITTR UHF ASK/FSK 310MHZ 24VQFN
• Manufacturer: Atmel

Specifications of ATA5773-PXQW

• Frequency: 310MHz ~ 350MHz
• Modulation Or Protocol: UHF
• Power - Output: 8dBm
• Voltage - Supply: 2 V ~ 4 V
• Current - Transmitting: 9.8mA
• Data Interface: PCB, Surface Mount
• Memory Size: 4kB Flash, 256B EEPROM, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Processor Series: ATA5x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

4.18.5
4.18.5.1
4.18.5.2
4.18.5.3
9137E–RKE–12/10
Register Descriptions
USIBR – USI Data Buffer
USIDR – USI Data Register
USISR – USI Status Register
The USI uses no buffering of the Serial Register, i.e., when accessing the Data Register
(USIDR) the Serial Register is accessed directly. If a serial clock occurs at the same cycle the
register is written, the register will contain the value written and no shift is performed. A (left)
shift operation is performed depending of the USICS1..0 bits setting. The shift operation can
be controlled by an external clock edge, by a Timer/Counter0 Compare Match, or directly by
software using the USICLK strobe bit. Note that even when no wire mode is selected
(USIWM1..0 = 0) both the external data input (DI/SDA) and the external clock input
(USCK/SCL) can still be used by the Shift Register.
The output pin in use, DO or SDA depending on the wire mode, is connected via the output
latch to the most significant bit (bit 7) of the Data Register. The output latch is open (transpar-
ent) during the first half of a serial clock cycle when an external clock source is selected
(USICS1 = 1), and constantly open when an internal clock source is used (USICS1 = 0). The
output will be changed immediately when a new MSB written as long as the latch is open. The
latch ensures that data input is sampled and data output is changed on opposite clock edges.
Note that the corresponding Data Direction Register to the pin must be set to one for enabling
data output from the Shift Register.
The Status Register contains Interrupt Flags, line Status Flags and the counter value.
• Bit 7 – USISIF: Start Condition Interrupt Flag
When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is
detected. When output disable mode or Three-wire mode is selected and (USICSx = 0b11 &
USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets the flag.
An interrupt will be generated when the flag is set while the USISIE bit in USICR and the
Global Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the
USISIF bit. Clearing this bit will release the start detection hold of USCL in Two-wire mode.
A start condition interrupt will wakeup the processor from all sleep modes.
Bit
0x10 (0x30)
Read/Write
Initial Value
Bit
0x0F (0x2F)
Read/Write
Initial Value
Bit
0x0E (0x2E)
Read/Write
Initial Value
USISIF
R/W
MSB
MSB
R/W
7
0
R
7
0
7
0
USIOIF
R/W
6
0
R/W
R
6
0
6
0
USIPF
R/W
5
0
R/W
R
0
5
5
0
USIDC
R
4
0
R/W
R
4
0
4
0
USICNT3
R/W
3
0
Atmel ATA5771/73/74
R/W
R
3
0
3
0
USICNT2
R/W
2
0
R/W
R
2
0
2
0
USICNT1
R/W
R/W
1
0
R
1
0
1
0
USICNT0
LSB
LSB
R/W
R/W
R
0
0
0
0
0
0
USIBR
USIDR
USISR
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