ATA5773-PXQW Atmel, ATA5773-PXQW Datasheet - Page 32

• Manufacturer Part Number: ATA5773-PXQW
• Description: XMITTR UHF ASK/FSK 310MHZ 24VQFN
• Manufacturer: Atmel

Specifications of ATA5773-PXQW

• Frequency: 310MHz ~ 350MHz
• Modulation Or Protocol: UHF
• Power - Output: 8dBm
• Voltage - Supply: 2 V ~ 4 V
• Current - Transmitting: 9.8mA
• Data Interface: PCB, Surface Mount
• Memory Size: 4kB Flash, 256B EEPROM, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Processor Series: ATA5x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

4.9
4.9.1
4.9.1.1
4.9.1.2
4.9.1.3
4.9.1.4
32
System Clock and Clock Options
Atmel ATA5771/73/74
Clock Systems and their Distribution
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
ADC Clock – clk
I/O
Figure 4-10 on page 32
tribution. All of the clocks need not be active at a given time. In order to reduce power
consumption, the clocks to modules not being used can be halted by using different sleep
modes, as described in
clock systems are detailed below.
Figure 4-10. Clock Distribution
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from perform-
ing general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is
also used by the External Interrupt module, but note that some external interrupts are detected
by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.
The Flash clock controls operation of the Flash interface. The Flash clock is usually active
simultaneously with the CPU clock.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O
clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC
conversion results.
CPU
ADC
FLASH
ADC
External Clock
clk
clk
ADC
I/O
Source clock
Section 4.10 “Power Management and Sleep Modes” on page
presents the principal clock systems in the Atmel
General I/O
System Clock
Modules
Control Unit
AVR Clock
Multiplexer
Prescaler
Clock
Calibrated RC
Oscillator
Oscillator
Crystal
Reset Logic
CPU Core
clk
clk
CPU
FLASH
Crystal Oscillator
Low-Frequency
Watchdog Timer
Watchdog clock
RAM
Watchdog
Oscillator
Flash and
EEPROM
Calibrated RC
®
Oscillator
AVR
®
9137E–RKE–12/10
and their dis-
41. The